A PLAN-TO-CLOSURE APPROACH HELPS ENSURE SILICON SUCCESS
Author: Cadence Design Systems (John Decker, Neyaz, and Richard Goering)
Introduction
The mandate to reduce system power consumption and design energy-efficient ICs has led to the
increasing use of low-power IC design techniques. In addition to well-established techniques like
clock gating, IC designers today are using advanced techniques such as power shutoff, back body
biasing, and dynamic voltage and frequency scaling (DVFS). More and more chips have multiple
operating modes as well as multiple power domains with different, and perhaps dynamically
variable, voltage levels.
The central problem with low-power verification is the explosion in scope and complexity caused by
low-power design techniques. Some chips today have 20 to 50 power domains and hundreds of
power modes. As a result, chips may have thousands or tens of thousands of possible power
states. Verification engineers must ensure that the chip functions correctly in each state that could
plausibly occur, and that all transitions between states are properly handled.
Because of this complexity, verification planning is essential for low-power designs. An ad-hoc
approach is not likely to succeed. The verification effort should start with a measurable, executable
plan that sets forth goals and priorities. This plan should guide verification efforts all the way to
verification closure, which occurs when goals are met. Along the way, low-power