16. Low Power Design Guide - Virage Logic: Minimizing Design Complexity with Power Physical IP

By Ken Brock, Product Marketing Director, Virage Logic

This chapter addresses minimizing low-power design complexity with poweroptimized IP. It covers information about Virage Logic (the semiconductor industry’s trusted IP partner), the power problem, and the complexity of designing with multiple power domains in SoC designs that contain memory and logic blocks. It also details the representation of low-power intent by means of the Common Power Format (CPF) for logic along with the Virage Logic power-optimized memory architecture and the CPF solution for memory: how CPF and memory models interact to make power optimization a reality.