Power management on chips has become a critical design factor.
Designers reduce dynamic and leakage power consumption of
mobile and wireless devices by employing various techniques
during the design implementation phase. The power dimension
to design closure presents significant new challenges besides the
usual concerns over design functionality, performance, and die
size. All designs at 65nm and beyond will utilize techniques such
as state retention flops, multiple voltage and power domains,
MTCMOS switch and DVFS. These techniques increase design
complexity and elevate the risk of an implementation mistake.
For example, the use of multiple voltage domains requires that
signals crossing the voltage domain boundaries be level-shifted
appropriately. The use of power domains in power-sensitive
designs requires that certain signals be isolated correctly under
the power-down condition. The presence of multiple voltage and
power domains leads to complex power and ground connectivity
issues on the chip that need to be checked. The EDA tools for
implementing and verifying these techniques are still evolving.
Implementation mistakes caught by late-stage power and
ground rail-aware simulations that take the design back to the
synthesis stage, can cost months. With the flow proposed in this
paper, such bugs can be expeditiously identified and resolved.