Verification of Low-Power Designs using CPF

The power wasted by leakage current can no longer be ignored in sub-micron designs. As the size of transistors shrink, the amount of current due to leakage rises exponentially. In order to minimize the power lost due to leakage, several design techniques have been developed. Functional defects can be introduced if these features designed to reduce power are either specified or implemented incorrectly. The problem is not only being able to detect these functional defects, but also being able to detect them early enough in the design cycle to avoid costly delays. This paper explains how CPF (Common Power Format) enabled tools can be used functionally verify that the features added to save power have not introduced defects. The paper will illustrate how the specification of design features such as Power Switch Off (PSO), Save Restore Registers (SR) and Isolation (ISO) can be verified at a RTL level and the advantages of using a CPF based flow over an ad-hoc solution.