As the electronics industry moves toward advanced CMOS process geometries at 65nm and below, considerable power management challenges have emerged that cannot be met by a design infrastructure optimized for 90nm and above. Throughout the design and manufacturing chain, there is a clear need for a holistic power-aware infrastructure that will enable design teams; ASIC, library, IP, and tool vendors; equipment providers; and silicon foundries alike to efficiently produce lower power electronics. The existing design infrastructure has had shortcomings in holistically communicating power-related design intent across the design flow. These limitations have prevented companies from initiating complex low-power projects due to high levels of risk and unpredictable design costs. The Power Forward Initiative was formed to address these obstacles to lower power IC design facing the electronics industry.

By Susan Runowicz-Smith, Group Director, Cadence Design Systems, Power Forward Initiative

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