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10. Low Power Design Guide - Sequence Design: Early Power Analysis with CPF


posted by Power Forward
07-30-2009

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10. Low Power Design Guide - Sequence Design: Early Power Analysis with CPF
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Tom Miller, Vice President and Head of R&D, Front-End Products, Sequence Design, Inc.

For power-efficient SoCs, designers must consider power throughout the design flow, particularly at higher levels of abstraction.  The chaper on "Front-End Design with CPF" clearly shows that the biggest power reductions occur during architectural tradeoffs.  The vast marjority of design work done in the industry starts at the RT level of abstraction, with ESL-based techniques gaining popularity.