09. Low Power Design Guide - Faraday: CPF-Based Low-Power Design Methodology for Platform-Based SoCs
07-30-2009
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09. Low Power Design Guide - Faraday: CPF-Based Low-Power Design Methodology for Platform-Based SoCs |
By Albert Chen, Field Applications and Marketing Manager, Faraday Technology Corp.
Low power has become a focal point for SoC designers. Advanced techniques such as multi-supply voltages, power gating, and dynamic voltage scaling are conceptually easy to understand, but difficult to implement in practice. Faraday, a top-tier ASIC service provider, offers successful low-power SoC designs across multiple market segments, using a proven, platform-based low-power methodology incorporating the Common Power Format (CPF) as a fundamental enabling technology.