Philip Watson, Implementation Environment Program Manager, ARM.
ARM and Cadence have been collaborating on low-power methodology development for a number of years to serve their common customers across all market segments, including wireless, consumer, computing, and networking.
In 2005, as fellow members of the Silicon Design Chain, ARM, and Cadence developed a low-power test chip that demonstrated 40% power savings compared to a standard timing closure flow. The design was based on ARM’s ARM1136JF-S test chip used in their RealView Integrator development boards. It was implemented using Artisan low-power technology libraries and was manufactured on a 90nm TSMC process.