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<?xml-stylesheet type="text/xsl" href="http://www.powerforward.org/utility/FeedStylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Power Forward Initiative (PFI) Community</title><link>http://www.powerforward.org/media/24/default.aspx</link><description>Articles</description><dc:language>en-US</dc:language><generator>CommunityServer 2008.5 (Build: 30929.2835)</generator><item><title>Power Forward Initiative Publishes On-Line Guide to Low-Power Design with the Common Power Format</title><link>http://www.powerforward.org/media/p/131.aspx</link><pubDate>Fri, 31 Jul 2009 16:36:26 GMT</pubDate><guid isPermaLink="false">2151c306-1704-4d62-833d-93f0cfd9f992:131</guid><dc:creator>Power Forward</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;Published in Chip Design April 30, 2008&lt;/p&gt;
&lt;p&gt;As the electronics industry moves toward advanced CMOS process
geometries at 65nm and below, considerable power management
challenges have emerged that cannot be met by a design infrastructure optimized
for 90nm and above. Throughout the design and manufacturing chain, there
is a clear need for a holistic power-aware infrastructure
that will enable design teams; ASIC, library, IP, and tool
vendors; equipment providers; and silicon foundries alike
to efficiently produce lower power electronics. The existing
design infrastructure has had shortcomings in holistically
communicating power-related design intent across the design
flow. These limitations have prevented companies from initiating
complex low-power projects due to high levels of risk and
unpredictable design costs. The Power Forward Initiative was
formed to address these obstacles to lower power IC design facing
the electronics industry.&lt;/p&gt;
&lt;p&gt;By Susan Runowicz-Smith, Group Director, Cadence Design Systems, Power Forward Initiative&lt;/p&gt;
&lt;p&gt;&lt;a target="_blank" href="http://www.chipdesignmag.com/cadence/display.php?article=1"&gt;&lt;b&gt;Read the full article here&lt;/b&gt;&lt;/a&gt; &amp;gt;&amp;gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description><enclosure url="http://www.chipdesignmag.com/cadence/display.php?article=1" length="-1" type="text/html" /></item><item><title>It's time to shift the low power debate</title><link>http://www.powerforward.org/media/p/129.aspx</link><pubDate>Fri, 31 Jul 2009 00:14:50 GMT</pubDate><guid isPermaLink="false">2151c306-1704-4d62-833d-93f0cfd9f992:129</guid><dc:creator>Power Forward</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Article published in SCD Source 4/15/2008&lt;/p&gt;
&lt;p&gt;In the low power debate over the last 18 months, much has been&amp;nbsp;written
about the EDA vendor battles between the two file formats used to
capture low-power design intent &amp;ndash; Common Power Format (CPF) and Unified
Power Format (UPF). The inability of these two standards efforts to
converge has frustrated a wide array of stakeholders up, down, and
across the supply chain.&lt;/p&gt;
&lt;h4 class="editor"&gt;By Steven E. Schulz, Si2&lt;/h4&gt;
&lt;p&gt;&lt;a target="_blank" href="https://cadencepfi.speaktech.com:443/media/g/articles/upload.aspx/In%20the%20low%20power%20debate%20over%20the%20last%2018%20months,%20much%20has%20been%20written%20about%20the%20EDA%20vendor%20battles%20between%20the%20two%20file%20formats%20used%20to%20capture%20low-power%20design%20intent%20&amp;ndash;%20Common%20Power%20Format%20(CPF)%20and%20Unified%20Power%20Format%20(UPF).%20The%20inability%20of%20these%20two%20standards%20efforts%20to%20converge%20has%20frustrated%20a%20wide%20array%20of%20stakeholders%20up,%20down,%20and%20across%20the%20supply%20chain."&gt;Read the full article here&lt;/a&gt; &amp;gt;&amp;gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description><enclosure url="http://www.scdsource.com/article.php?id=171" length="-1" type="text/html" /></item><item><title>A Practical Case Study In Low-Power Design Methodology</title><link>http://www.powerforward.org/media/p/124.aspx</link><pubDate>Thu, 30 Jul 2009 23:25:43 GMT</pubDate><guid isPermaLink="false">2151c306-1704-4d62-833d-93f0cfd9f992:124</guid><dc:creator>Power Forward</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Article published in &lt;i&gt;Electronic Product News&lt;/i&gt;.&lt;/p&gt;
&lt;p&gt;There can be little doubt that a majority of designers and managers
attending DATE this year will be searching for improved solutions to
low-power design requirements. While some may be neophytes, looking to
to better understand low-power concepts, terminology, and basic
techniques, many experts will be seeking proven capability and
interoperability supporting advanced techniques they understand but
cannot properly implement with traditional flows.&lt;/p&gt;
&lt;p&gt;By Steven E. Schulz, Silicon Integration Initiative&lt;/p&gt;
&lt;p&gt;&lt;a target="_blank" href="http://www.epn-online.com/page/new56459/a-practical-case-study-in-low-power-design-methodology.html"&gt;View the full article here&lt;/a&gt; &amp;gt;&amp;gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description><enclosure url="http://www.epn-online.com/page/new56459/a-practical-case-study-in-low-power-design-methodology.html" length="-1" type="text/html; charset=utf-8" /></item><item><title>It’s a Mixed-Signal World</title><link>http://www.powerforward.org/media/p/79.aspx</link><pubDate>Fri, 03 Jul 2009 23:56:39 GMT</pubDate><guid isPermaLink="false">2151c306-1704-4d62-833d-93f0cfd9f992:79</guid><dc:creator>Power Forward</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;&lt;i&gt;Article published in Low-power Design&lt;/i&gt;&lt;/p&gt;
&lt;p&gt;&lt;i&gt;Today it&amp;rsquo;s impossible to separate the analog and digital domains
without compromising essential system behaviour. Designers need to
adapt their modeling style for mixed-signal verification.&lt;/i&gt;&lt;/p&gt;
&lt;p class="author"&gt;Kishore Karnane, Product Marketing Director, Cadence&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description><enclosure url="http://low-powerdesign.com/cadence_karnane.htm" length="18906" type="text/html" /></item></channel></rss>