Power Forward Initiative (PFI) Community

Designing lean, green silicon machines

jprice — Sun, 28 Jun 2009 23:16:19 GMT

One of the most important engineering challenges of our time

Author: Cadence design Systems

Introduction

Everyone loves solar energy. It’s clean, renewable, and delivered free daily. However, it took millions of years for green plants to store the solar energy in the 1000 billion barrels of oil that existed on Earth when humans drilled the first oil well in 1858. Since then, we have burned up 750 billion of those barrels, and most of that consumption occurred in just the last 25 years. Together with burning coal, this rush to toss fossil fuels onto the bonfire has also released more carbon dioxide than the world’s oceans and forests can handle, trapping the sun’s rays in the atmosphere like greenhouse glass and leading to the climate change that now threatens everything from crops to coastlines. This is why finding ways to cut energy usage is one of the most important engineering challenges of our time. Cadence is at the forefront of this effort, developing new technologies to help engineers create green chip designs for energy-efficient electronic products.

BUILDING ENERGY-EFFICIENT ICs FROM THE GROUND UP

jprice — Sun, 28 Jun 2009 23:06:34 GMT

CONSIDERING LOW-POWER TECHNIQUES THROUGHOUT THE DEVELOPMENT PROCESS

Author: Cadence design Systems

Introduction

It’s easy to forget that mobile phones were a relatively rare sight just 15 years ago. Today, users quickly become disenchanted if their tiny devices don’t let them talk for hours between charges and play Internet videos without pause. The need to meet incessant consumer demand for more functionality in handheld devices is just one example of the many market forces driving innovation in ICs. The industry has also made phenomenal strides in performance and functionality in chips used to power everything from the servers behind the World Wide Web to TV set-top boxes that give viewers hundreds of channels and real-time playback.

POWER-AWARE VERIFICATION SPANS IC DESIGN CYCLE

jprice — Sun, 28 Jun 2009 22:59:31 GMT

A PLAN-TO-CLOSURE APPROACH HELPS ENSURE SILICON SUCCESS

Author: Cadence Design Systems (John Decker, Neyaz, and Richard Goering)

Introduction

The mandate to reduce system power consumption and design energy-efficient ICs has led to the increasing use of low-power IC design techniques. In addition to well-established techniques like clock gating, IC designers today are using advanced techniques such as power shutoff, back body biasing, and dynamic voltage and frequency scaling (DVFS). More and more chips have multiple operating modes as well as multiple power domains with different, and perhaps dynamically variable, voltage levels.

The central problem with low-power verification is the explosion in scope and complexity caused by low-power design techniques. Some chips today have 20 to 50 power domains and hundreds of power modes. As a result, chips may have thousands or tens of thousands of possible power states. Verification engineers must ensure that the chip functions correctly in each state that could plausibly occur, and that all transitions between states are properly handled.

Because of this complexity, verification planning is essential for low-power designs. An ad-hoc approach is not likely to succeed. The verification effort should start with a measurable, executable plan that sets forth goals and priorities. This plan should guide verification efforts all the way to verification closure, which occurs when goals are met. Along the way, low-power