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PSO Design Verification with IUS

Cadence — Thu, 10 Sep 2009 23:28:42 GMT

Agenda
• Low power and Power Shut Off (PSO)
• PSO verification challenges
• IUS support for PSO verification
• A verification example using IUS
• Summary

Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs

Cadence — Thu, 10 Sep 2009 23:27:11 GMT

Power management on chips has become a critical design factor.
Designers reduce dynamic and leakage power consumption of
mobile and wireless devices by employing various techniques
during the design implementation phase. The power dimension
to design closure presents significant new challenges besides the
usual concerns over design functionality, performance, and die
size. All designs at 65nm and beyond will utilize techniques such
as state retention flops, multiple voltage and power domains,
MTCMOS switch and DVFS. These techniques increase design
complexity and elevate the risk of an implementation mistake.
For example, the use of multiple voltage domains requires that
signals crossing the voltage domain boundaries be level-shifted
appropriately. The use of power domains in power-sensitive
designs requires that certain signals be isolated correctly under
the power-down condition. The presence of multiple voltage and
power domains leads to complex power and ground connectivity
issues on the chip that need to be checked. The EDA tools for
implementing and verifying these techniques are still evolving.
Implementation mistakes caught by late-stage power and
ground rail-aware simulations that take the design back to the
synthesis stage, can cost months. With the flow proposed in this
paper, such bugs can be expeditiously identified and resolved.

An Enhanced 90 Nanometer Power Optimization Methodology Applied to an ARM11 Processor-Based Design

Cadence — Thu, 10 Sep 2009 23:25:39 GMT

Development goals
• ARM 1136JF-S IC
– Power optimization methodology leverageable to synthesized digital
designs
– Collaborative development: Silicon design chain (Applied Materials,
ARM, Cadence, TSMC)
• ARM 1136JF-S IC PSO
– Power switch-off (PSO) enhancement: Methodology and
implementation
• ARM 1176JZF-S IC
– PSO and dynamic voltage and frequency scaling (DVFS)
enhancement: Methodology and implementation
– Facilitate comprehensive methodology across design, verification
and implementation
– Power Forward Initiative (Common Power Format, CPF)
– ARM, AMD, ATI, Applied Materials, Cadence, Calypto, Freescale, Fujitsu,
Golden Gate Technology, NEC Electronics, NXP, Sequence, TSMC

Low Power Methodology on a Multicore Networking chip

Cadence — Thu, 10 Sep 2009 23:22:54 GMT

Motivation
• Power is a limiting Factor in System Design
– Average Power Dissipation
– Peak Power Dissipation
• Peak Power a key concern in Line Powered Systems
– Thermal Dissipation in the system
– Reliability Issues

Formal Validation of Low-Power Designs

Cadence — Thu, 10 Sep 2009 23:19:13 GMT

Low-power chip designs are essential for today's portable devices as well as products that must conform to "green" initiatives. The most common techniques for controlling power, including power shut-off, clock gating, and multiple voltage domains, complicate the chip verification process. This paper discusses the intersection of these low-power design techniques and the use of formal analysis for verification. Topics covered include proper handling of assertions crossing power domain boundaries, use of formal analysis to verify power control modules (PCMs), and the role of Common Power Format (CPF) specification for formal analysis. This paper leverages the experience of several Cadence customers in using Incisive Formal Verifier (IFV) for PCM verification as well as assertion technology developed within Cadence.

Holistic Reusable Low-Power Specification for a Scalable Approach to Designing a Complex SoC

Cadence — Thu, 10 Sep 2009 23:17:37 GMT

Outline

A year ago …
CPF in action on SoC Platform
– New laws, new cells, new constraints
– Power Network representation & verification
– More complex Global signal distribution & STA
– Hierarchical use model of power intent format
– Scalable solution
A year later …

Low Power Design Challenges and Advance Techniques to Reduce Power at the Different Abstraction Levels and Looking in to Future.

Cadence — Thu, 10 Sep 2009 23:14:44 GMT

Topics

Introduction
Power Dissipation basic
Existing Low Power Techniques and Issues for
Advance LP Techniques (under exploration)

Verification of Low-Power Designs using CPF

Cadence — Thu, 10 Sep 2009 23:12:24 GMT

The power wasted by leakage current can no longer be ignored in sub-micron designs. As the size of transistors shrink, the amount of current due to leakage rises exponentially. In order to minimize the power lost due to leakage, several design techniques have been developed. Functional defects can be introduced if these features designed to reduce power are either specified or implemented incorrectly. The problem is not only being able to detect these functional defects, but also being able to detect them early enough in the design cycle to avoid costly delays. This paper explains how CPF (Common Power Format) enabled tools can be used functionally verify that the features added to save power have not introduced defects. The paper will illustrate how the specification of design features such as Power Switch Off (PSO), Save Restore Registers (SR) and Isolation (ISO) can be verified at a RTL level and the advantages of using a CPF based flow over an ad-hoc solution.

Fujitsu’s CPF Based Low Power Design Status and Today’s Power Format Conference Paper

Cadence — Thu, 10 Sep 2009 23:08:56 GMT

AGENDA

Fujitsu’s Low Power Design History and
Results
Fujitsu’s CPF Low Power Design Flow
CPF vs. UPF