Individual Chapters

16. Low Power Design Guide - Virage Logic: Minimizing Design Complexity with Power Physical IP

Power Forward — Fri, 25 Sep 2009 17:36:54 GMT

By Ken Brock, Product Marketing Director, Virage Logic

This chapter addresses minimizing low-power design complexity with poweroptimized IP. It covers information about Virage Logic (the semiconductor industry’s trusted IP partner), the power problem, and the complexity of designing with multiple power domains in SoC designs that contain memory and logic blocks. It also details the representation of low-power intent by means of the Common Power Format (CPF) for logic along with the Virage Logic power-optimized memory architecture and the CPF solution for memory: how CPF and memory models interact to make power optimization a reality.

15. Low Power Design Guide - Sonics: CPF Flow for Highly-Configurable On-Chip Network IP

Power Forward — Tue, 15 Sep 2009 21:07:26 GMT

By Scott Evans, Director of Software at Sonics, Inc.

Systems designers are moving rapidly toward using intelligent interconnect solutions in order to manage on-chip communications in system-on-chip (SoC) devices. This movement is seen most notably among multimedia, high performance networking and mobile applications.

Sonics was among the first to identify the need for an interconnect solution to address high performance systems and over the years established itself as the leading provider of intelligent On-chip Network solutions. Throughout this chapter, you will be introduced to the Sonics On-chip Network solutions and how Sonics, working along with Cadence® Design Systems, Inc. provides customers with the products and Common Power Format (CPF)-based supporting environment to accelerate low power designs.

14. Low Power Design Guide - ARM 1176-JZFS CPU-Based Low-Power Subsystem: Methodology to Reduce Electrical and Functional Failure in a Low-Power Design

Power Forward — Thu, 30 Jul 2009 23:32:31 GMT

By David Flynn, Fellow ARM; Sachin Idgunji, Architect, ARM; Felix Jen, Manager Design Implementation, UMC; Wen-Pin Lin, Senior Manager, UMC; and Vivek Shukla, Cadence Architect, Bangalore.

Leakage control has become a major design issue due to leakage currents that drain a battery’s charge even when a device is inactive or in standby mode. Transistors in each new process generation leak more than those in previous generations, due to transistor scaling effects, only exacerbating the problem.

13. Low Power Design Guide - AMD: Power Gating in a High-Performance GPU

Power Forward — Thu, 30 Jul 2009 23:29:59 GMT

Stuart Taylor, Physical Design Architect, and Henry Jen, Physical Design and Integration CAD Engineer, AMD.

AMD is a customer-centric innovation company, a processing powerhouse that offers smarter choices for its customers and makes technology more accessible to the world. AMD is focused on best meeting the needs of leading computing, wireless, and consumer electronics companies to help them deliver high-performance, energy-efficient, and visually realistic solutions.

12. Low Power Design Guide - When Do You Know You Have Saved Enough Power?

Power Forward — Thu, 30 Jul 2009 23:21:44 GMT

As everyone in wireless, consumer, multi-media, server, router, automotive and medical applications recognize, power consumption can be the key product differentiation and the key metric for success in the market. Three critical factors emerge:

• Peak power

• Average power

• Time required to switch between power mode

11. Low Power Design Guide - ARM Cortex iRM: CPF-Driven Low-Power Functionality in a High-Performance Design Flow

Power Forward — Thu, 30 Jul 2009 23:18:46 GMT

The following analysis of the ARM® Cortex™ processor CPF-driven low-power and high-performance design flow is based on a joint collaboration between Cadence and ARM. It focuses on the changes required to the design tool flow involved in implementing low power and multi-mode, multi-corner (MMMC). Multi-mode, multi-corner analysis and optimization ensures that the design is optimized across the complete range of voltages and frequencies. MMMC allows the user to work in multiple functional modes and operating corners concurrently.

10. Low Power Design Guide - Sequence Design: Early Power Analysis with CPF

Power Forward — Thu, 30 Jul 2009 23:09:26 GMT

Tom Miller, Vice President and Head of R&D, Front-End Products, Sequence Design, Inc.

For power-efficient SoCs, designers must consider power throughout the design flow, particularly at higher levels of abstraction. The chaper on "Front-End Design with CPF" clearly shows that the biggest power reductions occur during architectural tradeoffs. The vast marjority of design work done in the industry starts at the RT level of abstraction, with ESL-based techniques gaining popularity.

09. Low Power Design Guide - Faraday: CPF-Based Low-Power Design Methodology for Platform-Based SoCs

Power Forward — Thu, 30 Jul 2009 22:40:43 GMT

By Albert Chen, Field Applications and Marketing Manager, Faraday Technology Corp.

Low power has become a focal point for SoC designers. Advanced techniques such as multi-supply voltages, power gating, and dynamic voltage scaling are conceptually easy to understand, but difficult to implement in practice. Faraday, a top-tier ASIC service provider, offers successful low-power SoC designs across multiple market segments, using a proven, platform-based low-power methodology incorporating the Common Power Format (CPF) as a fundamental enabling technology.

08. Low Power Design Guide - ARM: 1176 IEM Reference Methodology

Power Forward — Thu, 30 Jul 2009 22:39:01 GMT

Philip Watson, Implementation Environment Program Manager, ARM.

ARM and Cadence have been collaborating on low-power methodology development for a number of years to serve their common customers across all market segments, including wireless, consumer, computing, and networking.

In 2005, as fellow members of the Silicon Design Chain, ARM, and Cadence developed a low-power test chip that demonstrated 40% power savings compared to a standard timing closure flow. The design was based on ARM’s ARM1136JF-S test chip used in their RealView Integrator development boards. It was implemented using Artisan low-power technology libraries and was manufactured on a 90nm TSMC process.

07. Low Power Design Guide - TSMC: Advanced Design for Low Power at 65nm and Below

Power Forward — Thu, 30 Jul 2009 22:37:00 GMT

By L.C. Lu, Deputy Director of the Design Methodology Program at TSMC, and David Lan, Senior Manager in design methodology at TSMC North America.

Several drivers create the need for low power today. These include advanced processes at 65nm and below, which, although they enable SoC designs with much more complexity, consume more power. Mobile devices also require low-power chips to extend the battery life in order to compete in the market place and also to reduce overall system cost, which includes packaging costs To achieve low-power, design for power has to be a goal from the start.

06. Low Power Design Guide - Freescale: Wireless Low-Power Design and Verification with CPF

Power Forward — Thu, 30 Jul 2009 22:35:04 GMT

By Milind Padhye, Low-Power Design Manager, and David Gross, Low-Power/ Wireless Tools and Methodology Manager, Freescale Semiconductor, Wireless. © Freescale Semiconductor.

Freescale is making the world a smarter place with leading embedded semiconductor solutions for cars, mobile phones, networks, and more. Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial, networking, and wireless markets. The privately held company is based in Austin, Texas, and has design, research and development, manufacturing, or sales operations in more than 30 countries. Freescale is one of the world’s largest semiconductor companies with 2007 sales of $5.8 billion. For mobile phones, Freescale delivers a full range of UMTS/WCDMA, EDGE, and GSM/GPRS platforms and components with a proven MXC Technology, the industry’s first single-core modem architecture.

05. Low Power Design Guide - NXP User Experience: Complex SoC Implementation with CPF

Power Forward — Thu, 30 Jul 2009 22:29:38 GMT

By Herve Menager, Architect, SoC Design Technology, NXP Semiconductors.

Founded by Philips, NXP is a top-10 semiconductor company creating semi-conductors, system solutions, and software that deliver better sensory experiences in mobile phones, personal media players, TVs, set-top boxes, identification applications, cars, and a wide range of other electronic devices.

04. Low Power Design Guide - Fujitsu: CPF in the Low-Power Design Reference Flow

Power Forward — Thu, 23 Jul 2009 23:36:15 GMT

By Tsutomu Nakamori, Manager of Low-Power Technology Development at Fujitsu. © Fujitsu 2008.

03. Low Power Design Guide: NEC Electronics: Integrating Power Awareness in SoC Design with CPF

Power Forward — Thu, 23 Jul 2009 23:25:51 GMT

By Toshiyuki Saito, Senior Manager, Design Engineering Development Division, NEC Electronics. ©NEC Electronics Corporation 2008.

02. Low Power Design Guide - ARC Energy PRO: Technology for Active Power Management

Power Forward — Thu, 23 Jul 2009 23:12:38 GMT

ARC Energy PRO offers technology for active power management that reduces power by as much as four-fold through an integrated hardware, software, and EDA flow based on the Common Power Format (CPF). It is ideal for battery-operated portable applications such as WiMAX, digital radio, medical devices, etc.

ARC currently offers two processor cores based on Energy PRO, and the technology will be an integral part of future processor cores, multimedia subsystems, and their applications.