2009 Silicon Valley Summit : Events

18. Track 2: Implementation and Signoff - Q & A Panel Video

Power Forward — Fri, 15 Jan 2010 15:31:51 GMT

Moderator: Anthony Williams, Cadence Design Systems

Panelists: : Bob Eisenstadt, Alchip; Albert Chen, Faraday Semiconductor; Robert Smith, Magma Design Automation; Ken Brock and Lisa Minwell, Virage Logic.

17a. Track 2: Implementation and Signoff - Magma Design Automation Video

Power Forward — Fri, 15 Jan 2010 15:26:29 GMT

TeraWatts to PicoWatts, A Low Power Perspective – Robert Smith, Magma Design Automation

15a. Track 2: Implementation and Signoff - Virage Logic Video

Power Forward — Fri, 15 Jan 2010 15:23:21 GMT

Power-Optimization using Standard Cell Logic Blocks – Ken Brock, Product Marketing Director, Virage Logic

14a. Track 2: Implementation and Signoff - Faraday Semiconductor Video

Power Forward — Fri, 15 Jan 2010 15:20:23 GMT

Power-Aware DFT & Test – Albert Chen, Field Applications and Marketing Manager, Faraday Semiconductor

13a. Track 2: Implementation and Signoff - Virage Logic Video

Power Forward — Fri, 15 Jan 2010 15:17:03 GMT

Implementation of Advanced Power-Aware Memory Compilers – Lisa Minwell, Director, Memory Product Marketing, Virage Logic

12. Track 1: Design and Verification - Q & A Panel

Power Forward — Fri, 15 Jan 2010 15:13:54 GMT

Moderator: Mike Carell, Cadence Design Systems

Panelists: Anmol Mathur, Calypto; Michael McNamara, Cadence Design Systems, Magdy Abadir, Freescale Semiconductor; Arvind Chopra, NXP; Scott Evans, Sonics.

11a. Track 1: Design and Verification - Sonics Audio

Power Forward — Fri, 15 Jan 2010 15:07:32 GMT

Supporting CPF for Highly-Configurable Interconnect IP – Scott Evans, Sonics

10a. Track 1: Design and Verification - MindTree Video

Power Forward — Fri, 15 Jan 2010 15:00:55 GMT

Power-Aware Interface – Santosh Shivadatta, Technical Director, MindTree

09a. Track 1: Design and Verification - Cadence Design Systems Video

Power Forward — Fri, 15 Jan 2010 14:56:40 GMT

High Level Synthesis Using C-to-Silicon Compiler: A Case Study of Control-Dominated Design – Michael McNamara, Cadence Design Systems

08a. Track 1: Design and Verification - Freescale Video

Power Forward — Fri, 15 Jan 2010 12:25:10 GMT

Freescale Low Power Design Challenges – Magdy Abadir, EDA Strategy, Vendor Relations, and Customer Collaborations, Freescale

07a. Track 1: Design and Verification - Calypto Video

Power Forward — Fri, 15 Jan 2010 12:20:19 GMT

Sequential Optimizations for Low Power Design – Anmol Mathur, CTO and co-founder, Calypto

06. Opening Session: Industry Insight Panel Video

Power Forward — Fri, 15 Jan 2010 11:53:31 GMT

Industry Insight Panel: The Low-Power Evolution - Challenges and Opportunities

Moderator: Richard Goering, Cadence Design Systems

Panelists: Steve Presant, AMD, Steve Carlson, Cadence, Scott Evans, Sonics, Ron Burns, Wipro

05a. Opening Session - Cadence Design Systems Video

Power Forward — Fri, 15 Jan 2010 11:46:21 GMT

Cadence Low-Power Solution: Spec to GDSII – Kumar Subramani, Architect, Cadence Design Systems

04. Opening Session - Cadence, ARM, UMC

Power Forward — Fri, 15 Jan 2010 11:43:27 GMT

Ulterior UMCL65SP ARM1176JZFSTM Low Power Results and Analysis – Sachin Idgunji, ARM;

Please send an email to info@powerforward.org for details.

03a. Opening Session – Si2 Video

Power Forward — Fri, 15 Jan 2010 11:30:06 GMT

Toward Interoperable Power Formats – Qi Wang, Vice Chair, TSG/LPG, Si2