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0. Practical Guide to Low-Power Design - Complete Guide
This is the complete Guide in Zip format. The members of PFI came together to devise, refine and...
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06/28/2009
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2,230
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12
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01. Low power Design Guide - Chapter 1: Introduction
It’s no secret that power is emerging as the most critical issue in system-on-chip (SoC) design...
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07/23/2009
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513
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4
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It’s a Mixed-Signal World
Article published in Low-power Design Today it’s impossible to separate the analog and digital...
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07/03/2009
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342
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0
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Low Power Design Challenges and Advance Techniques to...
Topics Introduction Power Dissipation basic Existing Low Power Techniques and Issues for Advance...
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09/10/2009
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263
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0
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POWER-AWARE VERIFICATION SPANS IC DESIGN CYCLE
A PLAN-TO-CLOSURE APPROACH HELPS ENSURE SILICON SUCCESS Author: Cadence Design Systems (John Decker...
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06/28/2009
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221
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0
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03. Low Power Design Guide: NEC Electronics: Integrating...
By Toshiyuki Saito, Senior Manager, Design Engineering Development Division, NEC Electronics. ©NEC...
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07/23/2009
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161
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1
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Verification of Low-Power Designs using CPF
The power wasted by leakage current can no longer be ignored in sub-micron designs. As the size...
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09/10/2009
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152
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0
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An Enhanced 90 Nanometer Power Optimization Methodology...
Development goals • ARM 1136JF-S IC – Power optimization methodology leverageable to...
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09/10/2009
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148
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0
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Designing lean, green silicon machines
One of the most important engineering challenges of our time Author: Cadence design Systems Introduction...
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06/28/2009
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146
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1
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PSO Design Verification with IUS
Agenda • Low power and Power Shut Off (PSO) • PSO verification challenges • IUS support...
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09/10/2009
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139
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0
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