|
13. Track 2: Implementation and Signoff - Virage Logic
Implementation of Advanced Power-Aware Memory Compilers – Lisa Minwell, Director, Memory Product...
|
01/13/2010
|
13
|
0
|
|
|
15. Track 2: Implementation and Signoff - Virage Logic
Power-Optimization using Standard Cell Logic Blocks – Ken Brock, Product Marketing Director...
|
01/13/2010
|
23
|
0
|
|
|
11. Track 1: Design and Verification - Sonics
Supporting CPF for Highly-Configurable Interconnect IP – Scott Evans, Sonics
|
01/13/2010
|
10
|
0
|
|
|
03. Opening Session – Si2
Toward Interoperable Power Formats – Qi Wang, Vice Chair, TSG/LPG, Si2
|
01/13/2010
|
12
|
0
|
|
|
10. Track 1: Design and Verification - MindTree
Power-Aware Interface – Santosh Shivadatta, Technical Director, MindTree
|
01/13/2010
|
11
|
0
|
|
|
17. Track 2: Implementation and Signoff - Magma Design Automation
TeraWatts to PicoWatts, A Low Power Perspective – Robert Smith, Magma Design Automation
|
01/13/2010
|
12
|
0
|
|
|
02. Opening Session - Global Unichip
GUC Low Power Design Platform - Albert Li, Global Unichip
|
01/13/2010
|
21
|
0
|
|
|
08. Track 1: Design and Verification - Freescale
Freescale Low Power Design Challenges – Magdy Abadir, EDA Strategy, Vendor Relations, and...
|
01/13/2010
|
17
|
0
|
|
|
14. Track 2: Implementation and Signoff - Faraday Semiconductor
Power-Aware DFT & Test – Albert Chen, Field Applications and Marketing Manager, Faraday...
|
01/13/2010
|
14
|
0
|
|
|
07. Track 1: Design and Verification - Calypto
Sequential Optimizations for Low Power Design – Anmol Mathur, CTO and co-founder, Calypto
|
01/13/2010
|
10
|
0
|