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18. Track 2: Implementation and Signoff - Q & A Panel...
Moderator: Anthony Williams, Cadence Design Systems Panelists: : Bob Eisenstadt, Alchip; Albert...
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01/15/2010
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32
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1
|
|
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17a. Track 2: Implementation and Signoff - Magma Design...
TeraWatts to PicoWatts, A Low Power Perspective – Robert Smith, Magma Design Automation
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01/15/2010
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19
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0
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|
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15a. Track 2: Implementation and Signoff - Virage Logic...
Power-Optimization using Standard Cell Logic Blocks – Ken Brock, Product Marketing Director...
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01/15/2010
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5
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0
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|
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14a. Track 2: Implementation and Signoff - Faraday Semiconductor...
Power-Aware DFT & Test – Albert Chen, Field Applications and Marketing Manager, Faraday...
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01/15/2010
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12
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0
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|
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13a. Track 2: Implementation and Signoff - Virage Logic...
Implementation of Advanced Power-Aware Memory Compilers – Lisa Minwell, Director, Memory Product...
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01/15/2010
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16
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0
|
|
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12. Track 1: Design and Verification - Q & A Panel
Moderator: Mike Carell, Cadence Design Systems Panelists: Anmol Mathur, Calypto; Michael McNamara...
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01/15/2010
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9
|
1
|
|
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11a. Track 1: Design and Verification - Sonics Audio
Supporting CPF for Highly-Configurable Interconnect IP – Scott Evans, Sonics
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01/15/2010
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14
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0
|
|
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10a. Track 1: Design and Verification - MindTree Video
Power-Aware Interface – Santosh Shivadatta, Technical Director, MindTree
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01/15/2010
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10
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0
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|
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09a. Track 1: Design and Verification - Cadence Design Systems...
High Level Synthesis Using C-to-Silicon Compiler: A Case Study of Control-Dominated Design –...
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01/15/2010
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18
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0
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08a. Track 1: Design and Verification - Freescale Video
Freescale Low Power Design Challenges – Magdy Abadir, EDA Strategy, Vendor Relations, and...
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01/15/2010
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23
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0
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