News : UMC

UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design

Power Forward — Thu, 30 Jul 2009 01:02:00 GMT

Cadence CPF-based Low Power Flow and Integrated DFM Capabilities Enable Simplified Advanced Node Design Methodology for UMC Customers

Hsin-Chu, Taiwan, 30 Jul 2009

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced today that it has delivered an end-to-end CPF-based low power and DFM-aware design, verification, and implementation solution tuned for semiconductor foundry UMC in support of its 40-nanometer process technology. The new reference flow provides designers with a reliable, UMC-validated methodology incorporating the latest in low power techniques and model-based DFM analysis and optimization capabilities for maximum power efficiency, superior quality of results, and accelerated yield ramp for advanced node designs.

“The Cadence methodology for UMC’s 40-nanometer process allows designers to create power-efficient chips using a single methodology that delivers consistent power intent all the way to production,” said Stephen Fu, director of the IP Development & Design Support Division at UMC. “In addition, the flow supports the UMC 40-nanometer process with advanced design-side DFM capabilities during physical implementation for lower risk and faster time to volume.”

The UMC reference flow employs the CPF-enabled Encounter® Digital Implementation (EDI) System and Cadence Low-Power Solution, and is aimed at efficient energy use and highest yield for 40-nm system-on-chip designs. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format and features power awareness throughout all necessary design steps, including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation and complete signoff analysis. CPF is an Si2-approved industry standard format for specifying power-saving techniques early in the design process, enabling sharing and reuse of low-power intelligence.

In addition to low power, the UMC reference flow also employs the Encounter Digital Implementation System’s full suite of integrated and foundry-certified model-based DFM capabilities for lithography. This enables designers to confidently prevent, analyze, and optimize for potential DFM hot-spots during the physical implementation flow in concert with other optimizations, including timing, signal integrity, area, power, and yield.

“The Cadence Low-Power Solution is unique, and our integrated DFM technologies are essential to advanced design methodologies today,” said Nitin Deo, group marketing director of Implementation Products at Cadence. “We are proud of our collaboration with UMC to provide the industry with a robust 40-nanometer design flow that delivers the most important requirements for designs today: performance, power efficiency, productivity, reliability and superior manufacturability.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:

Dan Holden
Cadence Design Systems, Inc.
408-944-7457
holden@cadence.com

Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Cadence Collaborates With UMC To Deliver 65nm CPF-Based Low-power Reference Design Flow

Power Forward — Mon, 09 Jun 2008 18:07:00 GMT

CPF-Based 65nm Low-Power Reference Design Flow Addresses Complex Design Issues and Accelerates High-Performance, Low-Power Designs

SAN JOSE, CA and HSINCHU, Taiwan, 09 Jun 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor foundry, today announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to the UMC 65-nanometer process. This reference flow enables customers to achieve optimal 65-nanometer low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.

This 65-nanometer low-power reference design flow uses UMC's "Leon" test chip as the reference design. Leon is an open source 32-bit RISC microprocessor core with other complex elements including SRAM. The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis. As proven with the Leon test chip, the combination of the 65-nanometer reference design flow and the UMC Low Power Kit enables increased productivity while managing design complexity, shortening time-to-market and reducing manufacturing risk.

The UMC 65-nanometer low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution, including Cadence Incisive® Unified Simulator for gate-level low-power simulation; Cadence Encounter® RTL Compiler for synthesis, low-power and DFT cell insertion; Encounter Conformal Low Power for equivalence checking and low power design implementation checking; Encounter Test for ATPG; SoC Encounter RTL-to-GDSII system for floorplanning, powerplan and place-and-route; Encounter Timing System for timing and SI signoff; Cadence QRC Extraction; VoltageStorm® PE for static power and IR analysis; and VoltageStorm DG and Virtuoso® UltraSim for dynamic analysis of current surge at power up. In addition, UMC's Low Power Kit, including its CPF-enabled library, was validated as part of the reference design flow development.

"We are working closely with Cadence to address complex design issues that face designers at 65 nanometers, while enabling faster time to volume through an integrated low-power solution," said Darsun Tsien, UMC's vice president of design methodology. "Through our ongoing collaboration with Cadence, we are able to provide designers with validated low-power technologies to manage power concerns and meet aggressive time-to-market goals."

"This CPF-based flow, the result of a joint effort between Cadence and UMC, accelerates implementation of low-power designs," said Chi-Ping Hsu, corporate vice president of IC Digital and Power Forward at Cadence. "The combination of UMC process technology and the Cadence Low-Power Solution provides our mutual customers with the ability to realize their aggressive project goals while preserving low-power intent throughout the design process."

About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC's SoC Solution Foundry strategy is based on the strength of the company's advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 13,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at www.umc.com.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:

Sophy Shen
Direct:+886.3.566.3834
sophys@cadence.com
Cadence Design Systems, Inc.

Alex Hinnawi
Direct:(886) 2.2700.6999 ext. 6958
UMC

Eileen Elam
Direct:408-927-7753
eileen@kjcompr.com
KJ Communications (for UMC in the U.S.)

Cadence, Encounter, Incisive, Conformal, Virtuoso and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks, of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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UMC Joins Power Forward Initiative To Make Low-Power Design Easier

Power Forward — Tue, 17 Apr 2007 02:07:00 GMT

SAN JOSE and HSINCHU, TAIWAN, 17 Apr 2007

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that global semiconductor foundry UMC (NYSE: UMC, TSE: 2303) has joined the Power Forward Initiative (PFI). The Initiative, made up of more than 20 industry-leading electronics companies, was formed in May 2006 to advance the adoption of the Common Power Format (CPF) which captures essential design intent for power and links the design, implementation and verification domains.

"UMC has developed one of the industry's most comprehensive low-power solution packages to help our customers effectively design for low-power and power- management applications targeting the consumer, wireless and communication segments," said Patrick Lin, SoC chief architect at UMC. "In order to extend our expertise to support broader, industry-wide low-power efforts, we have joined the Power Forward Initiative and expect that the Common Power Format will streamline the entire low-power design process to help customers accelerate the migration to advanced process nodes."

"It is important for foundries and design software and IP providers to work closely together to address the issue of low-power design," said Jan Willis, senior vice president of Industry Alliances at Cadence. "We applaud UMC's leadership and commitment to invest their resources to support the work of the Power Forward Initiative. The continued momentum of the Initiative speaks to the importance of making low-power design easier at advanced technology nodes."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC's SoC Solution Foundry strategy is based on the strength of the company's advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

About Power Forward Initiative
The Power Forward Initiative, which has more than 20 member companies, is an industry initiative sponsored by Cadence and has the goal of enabling the design and production of more power-efficient electronic devices. The Advisory Group consists of representative companies across the design chain from microprocessors to IP to foundries and semiconductor companies and includes four EDA companies including Cadence. CPF v1.0 was contributed by Cadence to the Si2 Low Power Coalition in December 2006 and is now available as an Si2 standard to the industry at large.

For more information, please contact:

Michael Fournell
direct:408.428.5135
fournell@cadence.com
Cadence Design Systems, Inc.
Eileen Elam
direct:408.927.7753
eileen@kjcompr.com
KJ Communications
UMC (US)
Alex Hinnawi
direct:+886.2.2700.6999 ext. 6958
alex_hinnawi@umc.com
UMC (Taiwan)

Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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