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Newshttp://www.powerforward.org/home/news/default.aspxenCommunityServer 2008.5 (Build: 30929.2835)Cadence Design Systems to Host Second Annual Silicon Valley Power Forward Low-Power Design Summithttp://www.powerforward.org/home/news/archive/2009/10/15/182.aspxThu, 15 Oct 2009 12:33:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:182admin0<p><b>San Jose, Calif., 15 Oct 2009</b></p> <p><b>What:</b><br />Power Forward Low-Power Design Summit <br /><br /><b>When:</b><br />20 October 2009<br />8:30 am to 6:00 pm <br /><br /><b>Where:</b><br />Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134 <br />Building 10 R&D Auditorium <br /><br /><b>Press Registration:</b><br />Contact Niki Tran at <a href="mailto:%20nikitran@cadence.com">nikitran@cadence.com</a> or (408) 428-5159 <br /><br />Member companies of the Power Forward Initiative (PFI) and others will share their low-power design expertise, including best practices and proven capabilities that engineers can adopt to design energy-efficient wireless and wired electronics. </p> <ul class="productList"> <li class="productListItem">Interact with presenters and panelists in sessions focusing on design experiences, low-power IP, and architectural design topics;</li> <li class="productListItem">Hear about ecosystem capabilities including advanced solutions that support a holistic low-power design methodology;</li> <li class="productListItem">Discuss emerging low-power design techniques and learn about the trends for future power efficient and ‘green’ technologies.</li> </ul> <p><b>Agenda:</b></p> <table cellpadding="0" cellspacing="4"> <tbody> <tr> <td>8:30</td> <td>Registration and breakfast</td> </tr> <tr> <td>9:00</td> <td>Welcome and introduction</td> </tr> <tr> <td>9:20</td> <td>PFI members technical presentations<br />GUC<br />Si2<br />ARM<br />Cadence</td> </tr> <tr> <td>11:30</td> <td>Industry Insight Panel <br />Panelists: Wipro, Sonics, Cadence, AMD</td> </tr> <tr> <td>12:00</td> <td>Lunch</td> </tr> <tr> <td>1:00</td> <td>Technical presentations (Parallel tracks) <table cellpadding="3" cellspacing="1" style="background-color:#ccc;"> <tbody> <tr> <td style="background-color:#ccc;">Design and verification</td> <td style="background-color:#ccc;">Implementation and signoff</td> </tr> <tr> <td style="background-color:#fff;">Calypto </td> <td style="background-color:#fff;">Virage </td> </tr> <tr> <td style="background-color:#eee;">Freescale</td> <td style="background-color:#eee;">Faraday</td> </tr> <tr> <td style="background-color:#fff;">Cadence</td> <td style="background-color:#fff;">Virage </td> </tr> <tr> <td style="background-color:#eee;">Mindtree</td> <td style="background-color:#eee;">Alchip </td> </tr> <tr> <td style="background-color:#fff;">Sonics</td> <td style="background-color:#fff;">Magma </td> </tr> <tr> <td style="background-color:#eee;">Q&A panel</td> <td style="background-color:#eee;">Q&A panel</td> </tr> <tr> <td style="background-color:#fff;">Panelists: Above member companies + NXP</td> <td style="background-color:#fff;">Panelists: Above member companies</td> </tr> </tbody> </table> </td> </tr> <tr> <td>4:15</td> <td>Closing remarks/Raffle (Amazon Kindle, PFI Low-Power Guide)</td> </tr> <tr> <td style="background-color:#fff;">4:30</td> <td style="background-color:#fff;">Networking/drinks/hors d'oeuvres</td> </tr> </tbody> </table> <p><i>This schedule is subject to change</i></p> <div></div> <div class="ExternalClass3A9FEF73E5BD43A185F2A86557F9B182"><br /><b>About the Power Forward Initiative</b><br />The Power Forward Initiative, which has more than 40 member companies, is an industry initiative sponsored by Cadence Design Systems (NASDAQ: CDNS) and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. The Common Power Format (CPF) was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a target="_blank" href="http://www.powerforward.org/">www.powerforward.org</a>. </div> <p><br /><b>For more information, please contact:</b></p> <div class="ExternalClass5510A04367A9467EB55CD5CD636C9F62"> <div>Dan Holden<br />Power Forward Initiative<br />408-960-5159<br /><a href="mailto:holden@cadence.com">holden@cadence.com</a> </div> </div><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=182" width="1" height="1">S3 Joins Power Forward Initiativehttp://www.powerforward.org/home/news/archive/2009/10/07/180.aspxWed, 07 Oct 2009 20:54:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:180admin0<p><strong>San Jose, Calif., 1st October, 2009</strong></p> <p>Silicon & Software Ltd. (S3), a worldwide leading provider of design services, consultancy and software products to the semiconductor industry, the digital TV industry and the telehealth industry, today announced that it has joined the Power Forward Initiative (PFI). Established by Cadence Design Systems, Inc. and its partners to develop comprehensive approaches to power-efficient design, PFI now welcomes S3 as the organization continues to advance low power standards and solutions. <br /><br />S3 has been focused on low power design for over 20 years, and has a heritage of contributing to power standards for wireless design, from the Digital Enhanced Cordless Telecommunications (DECT) standard to the Long Term Evolution (LTE) standard for radio technologies. The company has full analog-digital-RF SoC architecture, design and verification capabilities. S3 has also developed advanced low power methodologies to automate design techniques such as voltage islands and voltage gating in nanometer nodes, which it has been applying since 2004. Recently, S3 integrated the Common Power Format (CPF) into its proprietary NanoFlow environment, thereby reducing risk and accelerating time to market for low power designs. S3's design services expertise is complemented by an extensive portfolio of silicon-proven power management products including Mixed Signal IP (DC/DC, Linear Regulators, and Power Switches). <br /><br />"We are happy to bring our low power implementation knowledge, and experience, including multiple tapeouts at leading edge geometries, to help address the common goals of the PFI. We are looking forward to making what we hope will be valuable contributions to the initiative," said James Blair, Director of Consumer Silicon Services, S3. <br /><br />"It is a pleasure to welcome S3, with such a strong legacy in the IC design industry, into the Power Forward Initiative," said Steve Carlson, vice president of Low Power Solutions marketing at Cadence. "With the addition of S3 the Power Forward Initiative has grown to over 40 highly reputable members, all of whom are delivering on our common goal of bringing high-quality, low power methodologies, solutions, services and silicon to customers globally." <br /><br /><b>About Silicon & Software Systems Ltd. (S3):</b><br />S3 is the Connected Consumer Technology Company, providing semiconductor design services, semiconductor IP, software products, and systems knowledge expertise for its global client base competing in fast-moving consumer electronics as well as wired and wireless communications markets. S3's technologies, products and professional services enable semiconductor companies, consumer electronics companies and healthcare providers to deliver next-generation devices, systems and services to consumers at home and on the move. For IC designers and product managers, S3 delivers a comprehensive portfolio of mixed-signal IP and design services for power-efficient single-chip systems. S3's System-on-Chip customers are repeat users, who benefit from having the confidence to meet tight time-to-market schedules with reduced design risk. S3's mixed signal IP includes a wide portfolio of high performance A/D and D/A convertors, PLLs, Analog Front Ends (AFEs), Power Management and other miscellaneous circuits which have been silicon proven at a number of merchant foundries (TSMC, UMC, Chartered, IBM, Tower, SMIC) at nodes ranging from 0.18um to 65nm. Founded in 1986, S3 has design centers in Ireland (Dublin and Cork), Lisbon in Portugal, Wroclaw in Poland, Prague in the Czech Republic and San Jose in the USA with sales offices and representatives globally. For further information please visit www.s3group.com or email us at info(at)s3group.com. <br /><br /><b>Contacts:</b><br />Fiona D'Arcy, Silicon & Software Systems (S3)<br />Tel: +353.87.2808828 Email: fiona.darcy(at)s3group.com <br /><br /><b>About Power Forward Initiative:</b><br />The Power Forward Initiative, which has more than 40 member companies, is an industry initiative sponsored by Cadence Design Systems (NASDAQ: CDNS) and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. The Common Power Format (CPF) was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at www.powerforward.org. <br /><br /><strong>Contacts:<br /></strong>Dan Holden <br />Power Forward Initiative<br />1-408-944-7457 <br /><a href="mailto:%20holden@cadence.com">holden@cadence.com</a> <br /><br /><em>All trademarks contained herein (whether registered or not) and all associated rights are recognized.</em></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=180" width="1" height="1">Cadence Low-Power Solution Selected for Global Unichip’s PowerMagic Low-Power Design Methodologyhttp://www.powerforward.org/home/news/archive/2009/08/17/175.aspxMon, 17 Aug 2009 08:20:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:175admin0<table id="CadenceProduct_MainTable" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;" cellpadding="0" cellspacing="0"> <tbody> <tr id="TopRow"> <td id="TopCell"> <div style="padding-right:1px;padding-left:1px;"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td id="MSOZoneCell_WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td> <div id="WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621" class="ms-WPBody"> <div id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"> <div id="body_text" style="padding-left:15px;padding-right:15px;"><b>PowerMagic 65-Nanometer Design Methodology Leverages Cadence End-to-End CPF-Based Low-Power Solution</b><br /><br /><b>SAN JOSE, Calif., 17 Aug 2009</b><br /><br /> <div class="ExternalClass0EECAF93756346B9BFD11B252E957FAA">Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Global Unichip Corporation (GUC) has integrated the CPF-based <a href="http://www.cadence.com/solutions/lp/Pages/Default.aspx">Cadence Low-Power Solution</a> into its PowerMagicTM methodology to optimize the design of its customers’ complex low-power ASIC implementations in advanced technology. <br /><br />GUC was able to develop a complete end-to-end low power ASIC flow, including dynamic voltage frequency scaling (DVFS) techniques, by integrating the Cadence® Low-Power Solution, including Cadence Encounter® RTL Compiler, <a href="http://www.cadence.com/products/di/Pages/default.aspx">Encounter Digital Implementation System</a> and Encounter Conformal® Low Power, together with its proprietary in-house tools, into the PowerMagic methodology for design, verification, and implementation. These techniques are keys to enabling multiple power domains of variable voltages on a single chip and reducing voltage to circuits when peak performance is not required. <br /><br />“Our designers benchmarked the capabilities of the Cadence Low-Power Solution by optimizing a 65-nanometer, 10-million-gate low power design while correctly implementing more than ten power domains and over 50 power modes,” said C.C. Hsieh, vice president of Design Service at GUC. “Cadence low power solutions worked well in GUC’s integrated PowerMagic methodology, which effectively resolved low power implementation and verification issues that puzzled ASIC designers in a complex low power design project.” <br /><br />The Cadence Low-Power Solution provides a complete methodology for design-to-signoff that begins with early design planning and includes front-end design, synthesis and physical implementation. It enables consistency and convergence through power estimation and analysis at every step. Alongside the implementation flow, comprehensive power verification is performed by leveraging static, dynamic and formal power verification techniques in a closed-loop verification methodology. This fully integrated, highly automated, power-aware solution is backed by industry-leading services capabilities and the industry's largest power-focused industry alliances – the Power Forward Initiative and Si2's Low Power Coalition. <br /><br />“By implementing the Cadence Low-Power Solution in its PowerMagic methodology for low-power design, GUC has delivered a tremendous productivity and quality boost to its design teams intent on providing superior low-power circuits to its customers,” said Chi-Ping Hsu, senior vice president of digital implementation research and development at Cadence. “The combination should provide tremendous value to GUC’s customers.” </div> <div class="ExternalClass79CF64C73F3B482E8BB5F6CBEF38D86F"><br /><b>About Cadence</b><br />Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at <a href="http://www.cadence.com/">www.cadence.com</a>. <br /><br /><b>About GUC</b><br />Global Unichip Corp. (GUC), a dedicated full service SoC (System On Chip) Design Foundry based in Taiwan, was founded in 1998. GUC is now publicly traded on the Taiwan Stock Exchange under the symbol 3443 with 2008 revenue of 295MUSD. GUC provides total solutions from silicon-proven IPs to complex time-to-market SoC turnkey services. GUC is committed to providing the most advanced and the best price-performance silicon solutions through close partnership with TSMC, GUC’s major shareholder, and other key packaging and testing power houses. With state of the art EDA tools, advanced methodologies, and experienced technical team, GUC ensures the highest quality and lowest risks to achieve first silicon success. GUC has established a global customer base throughout Greater China, Japan, Korea, North America, and Europe. Its track-record in complex SoC designs has brought benefits to customers in time to revenue at the lowest risk. For more information about GUC please see <a href="http://www.globalunichip.com/" target="_blank">www.globalunichip.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass022AC553C7214F138D5A7C458126C856"> <div>Dan Holden<br />Cadence Design Systems, Inc.<br />(408) 944-7457 <br /><a href="mailto:holden@cadence.com">holden@cadence.com</a></div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClass974D249DA4744536B9FDF3B72E0B1182">Cadence,the Cadence logo, Encounter, and Conformal are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners. </div> </span></div> </span> </div> </div> </td> </tr> </tbody> </table> </td> </tr> </tbody> </table> <div class="topbanner" id="Zone_Template_1_image_area"> </div> </div> </td> </tr> <tr id="MiddleRow"> <td id="CadenceProdSoluMainContent" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;"></td> </tr> </tbody> </table><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=175" width="1" height="1">newsCPFUMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Designhttp://www.powerforward.org/home/news/archive/2009/07/30/114.aspxThu, 30 Jul 2009 01:02:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:114Power Forward0<table id="CadenceProduct_MainTable" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;" cellpadding="0" cellspacing="0"> <tbody> <tr id="TopRow"> <td id="TopCell"> <div style="padding-right:1px;padding-left:1px;"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td id="MSOZoneCell_WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td> <div id="WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621" class="ms-WPBody"> <div id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"> <b>Cadence CPF-based Low Power Flow and Integrated DFM Capabilities Enable Simplified Advanced Node Design Methodology for UMC Customers</b><br /><br /><b>Hsin-Chu, Taiwan, 30 Jul 2009</b><br /><br /> <div class="ExternalClassA8D84C4F973946A384B493B6A28CCB5E">Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced today that it has delivered an end-to-end CPF-based low power and DFM-aware design, verification, and implementation solution tuned for semiconductor foundry UMC in support of its 40-nanometer process technology. The new reference flow provides designers with a reliable, UMC-validated methodology incorporating the latest in low power techniques and model-based DFM analysis and optimization capabilities for maximum power efficiency, superior quality of results, and accelerated yield ramp for advanced node designs. <br /><br />“The Cadence methodology for UMC’s 40-nanometer process allows designers to create power-efficient chips using a single methodology that delivers consistent power intent all the way to production,” said Stephen Fu, director of the IP Development & Design Support Division at UMC. “In addition, the flow supports the UMC 40-nanometer process with advanced design-side DFM capabilities during physical implementation for lower risk and faster time to volume.” <br /><br />The UMC reference flow employs the CPF-enabled <a href="http://www.cadence.com/products/di/Pages/default.aspx">Encounter® Digital Implementation (EDI) System</a> and <a href="http://www.cadence.com/solutions/lp/Pages/Default.aspx">Cadence Low-Power Solution</a>, and is aimed at efficient energy use and highest yield for 40-nm system-on-chip designs. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format and features power awareness throughout all necessary design steps, including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation and complete signoff analysis. CPF is an Si2-approved industry standard format for specifying power-saving techniques early in the design process, enabling sharing and reuse of low-power intelligence. <br /><br />In addition to low power, the UMC reference flow also employs the Encounter Digital Implementation System’s full suite of integrated and foundry-certified model-based DFM capabilities for lithography. This enables designers to confidently prevent, analyze, and optimize for potential DFM hot-spots during the physical implementation flow in concert with other optimizations, including timing, signal integrity, area, power, and yield. <br /><br />“The Cadence Low-Power Solution is unique, and our integrated DFM technologies are essential to advanced design methodologies today,” said Nitin Deo, group marketing director of Implementation Products at Cadence. “We are proud of our collaboration with UMC to provide the industry with a robust 40-nanometer design flow that delivers the most important requirements for designs today: performance, power efficiency, productivity, reliability and superior manufacturability.” </div> <div class="ExternalClass144FC17E15554B539AEC2D6D84862AB1"><br /><b>About Cadence</b><br />Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at <a href="http://www.cadence.com/">www.cadence.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass67177254FEBC44CE87F792E0F7353D2F"> <div>Dan Holden<br />Cadence Design Systems, Inc.<br />408-944-7457<br /><a href="mailto:holden@cadence.com">holden@cadence.com</a></div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClass5965C0C638F44747941A9421C23B6EAD">Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.</div> </span></span></div> </div> </td> </tr> </tbody> </table> </td> </tr> </tbody> </table> <div class="topbanner" id="Zone_Template_1_image_area"> </div> </div> </td> </tr> <tr id="MiddleRow"> <td id="CadenceProdSoluMainContent" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;"> </td> </tr> </tbody> </table><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=114" width="1" height="1">newsLow powerCPFUMCCadenceCadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0http://www.powerforward.org/home/news/archive/2009/07/23/141.aspxThu, 23 Jul 2009 16:07:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:141Power Forward0<table id="CadenceProduct_MainTable" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;" cellpadding="0" cellspacing="0"> <tbody> <tr id="TopRow"> <td id="TopCell"> <div style="padding-right:1px;padding-left:1px;"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td id="MSOZoneCell_WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td> <div id="WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621" class="ms-WPBody"> <div id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"> <div id="body_text" style="padding-left:15px;padding-right:15px;"><b>Cadence Innovations in Low Power, Statistical and DFM Analysis, Advanced-Node Design and SiP Deliver Fast Time to Volume for Users of TSMC Process Technology</b><br /><br /><b>SAN JOSE, Calif., 23 Jul 2009</b><br /><br /> <div class="ExternalClassABD8B1DFB78945EFA6E4E78ECCF6B7E7">Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that its suite of Cadence® Encounter® Digital Implementation System solutions, including design closure, low power, DFM, mixed signal, and signoff technologies, as well as Cadence System-In-Package design technology are included in TSMC Reference Flow 10.0. The RTL-to-GDSII design capabilities in the Cadence track enable designers to produce high-yielding, power-efficient designs for the foundry’s most advanced manufacturing processes. <br /><br />“Reference Flow 10.0 plays a critical role in design enablement for new process technologies,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. “The close collaboration with Cadence ensures needed tool enhancements are made ahead of time, as we are entering 28 nanometers.” <br /><br />“Providing best-in-class solutions for today’s toughest design challenges and developing solutions ahead of the curve for tomorrow requires continuous innovation and tight collaboration with our customers and business partners,” said Dr. Chi Ping Hsu, vice president of digital implementation research and development at Cadence. “Working closely with TSMC helps ensure our leadership in low-power, mixed-signal, integrated DFM, advanced-node, and signoff technologies, and enables Cadence to provide a complete and predictable solution from RTL to final silicon.” <br /><br /><b>DFM, Digital Implementation and Analysis</b><br />A key contribution to Reference Flow 10.0 is the industry’s first context-aware electrical analysis of library cell and SOC designs. Using the award-winning Cadence Litho Electrical Analyzer, designers can electrically fine-tune library cells and accurately model electrical stress effects, thereby increasing product quality. In addition, the hierarchical Litho Physical Analyzer produces fast analysis of the physical manufacturability of nanometer-level devices. Both of these unique DFM capabilities are integrated into the Encounter Digital Implementation System, allowing early design stage identification, analysis and repair of potential manufacturing issues. <br /><br />Other variation reduction techniques covered under the Cadence track of TSMC Reference Flow 10.0 include statistical static timing analysis (SSTA), placement optimization, advanced clock tree analysis and on-chip variation analysis. All of these techniques are dramatically accelerated through end-to-end support for multi-processor–based computing platforms. <br /><br />Building upon the Cadence NanoRoute® Router, which significantly boosts designer productivity and accelerates overall turnaround time, Cadence delivers a variety of other DFM techniques, including physical defect analysis, virtual CMP hot spot analysis, lithography process checking, advanced process modeling, and substrate noise analysis. All of these capabilities are fully integrated into the Encounter Digital Implementation System to allow the closest possible correlation between optimization and signoff. <br /><br /><b>Advanced Low-Power Design</b><br />Cadence introduced its Low-Power Design Solution more than two years ago and immediately incorporated its features into the TSMC Reference Flow 8.0. Since then, Cadence has updated its Low-Power Solution with new capabilities, including hierarchical support for the Si2 Common Power Format (CPF), pulse-latch, and dual-flop solutions. Because the Cadence Low-Power Solution is also seamlessly integrated into the Encounter Digital Implementation System, it provides low cost of ownership and an easy-to-use design environment for low-power design. <br /><br />Cadence track of TSMC Reference Flow 10.0 <ul class="productList"> <li class="productListItem">Encounter Digital Implementation System (EDI System)</li> <li class="productListItem">Cadence Low-Power Solution</li> <li class="productListItem">Encounter RTL Compiler</li> <li class="productListItem">Encounter Test </li> <li class="productListItem">Encounter Conformal® (Low Power, Constraint Designer, LEC)</li> <li class="productListItem">First Encounter Silicon Virtual Prototyping</li> <li class="productListItem">NanoRoute Router</li> <li class="productListItem">Encounter Timing System (with CeltIC® NDC) </li> <li class="productListItem">Encounter Power System</li> <li class="productListItem">QRC Extraction</li> <li class="productListItem">Encounter Library Characterizer</li> <li class="productListItem">Cadence SiP Digital Architect</li> <li class="productListItem">Cadence SiP Digital Layout</li> <li class="productListItem">Litho Physical Analyzer </li> <li class="productListItem">Litho Electrical Analyzer </li> <li class="productListItem">Cadence CMP Predictor </li> <li class="productListItem">Virtuoso® Digital Implementation</li> <li class="productListItem">SoC Encounter™ System</li> <li class="productListItem">VoltageStorm® Power Verification</li> </ul> </div> <div class="ExternalClass3E2C3AF59C6746F5B2C652FC00C88110"><br /><b>About Cadence</b><br />Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at <a href="http://www.cadence.com/">www.cadence.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClassA9C4BA0A399B463ABEFD5AF88AAD19C0"> <div>Dan Holden <br />Cadence Design Systems, Inc. <br />direct: 408.944.7457 <br /><a href="mailto:holden@cadence.com">holden@cadence.com</a></div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClass30E7D807A4914501ACD9788B509924DE">Cadence, NanoRoute, Encounter, Conformal, Virtuoso, VoltageStorm and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.</div> </span></div> </span> </div> </div> </td> </tr> </tbody> </table> </td> </tr> </tbody> </table> <div class="topbanner" id="Zone_Template_1_image_area"> </div> </div> </td> </tr> <tr id="MiddleRow"> <td id="CadenceProdSoluMainContent" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;"></td> </tr> </tbody> </table><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=141" width="1" height="1">newsTSMCRicoh Joins Power Forward Initiativehttp://www.powerforward.org/home/news/archive/2009/07/15/81.aspxWed, 15 Jul 2009 04:00:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:81Power Forward0<p><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"><b>Ecosystem Continues Expansion; Cadence Low-Power Solution Delivers Improved Productivity In Consecutive Ricoh Tapeouts</b><br /><br /><b>SAN JOSE, Calif., 15 Jul 2009</b><br /><br /> <div class="ExternalClass0A32B1216019498C8D02DB06EA241CCB">Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced today that Ricoh Co., Ltd. has joined the <a href="http://www.cadence.com/Alliances/power_forward/pages/default.aspx">Power Forward Initiative</a> after completing two complex power management system-on-chip (SoC) designs using the <a href="http://www.cadence.com/products/lp/Pages/Default.aspx">Cadence® Low-Power Solution</a>. As a result of this success, Ricoh is driving the use of the Common Power Format (CPF)-enabled low-power methodology. Membership in the Power Forward Initiative also enables Ricoh to contribute directly to the improvement of low-power design technology. <br /><br />“The complexity of our chip designs, and the associated market requirements, demand that we use the best technologies and methodologies available,” said Fumiaki Kadowaki, manager of the CAD Engineering Section, Imaging System LSI Development Center, Electronic Devices Company at Ricoh. “The completeness of the Cadence automated solution for designing power shut-off and multiple supply/multiple power domains provided productivity benefits and greatly reduced risk versus traditional approaches.” <br /><br />The Cadence Low-Power Solution enables power shut-off simulation using the Incisive® Enterprise Simulator; automated power shut-off and multi-supply voltage synthesis using Encounter® RTL Compiler global synthesis; and comprehensive verification using the Encounter Conformal® Low Power solution. In addition, the Encounter Digital Implementation System offers a comprehensive floorplanning, prototyping, placement, routing and sign-off solution for challenging low-power designs. The low-power design methodology leverages the Common Power Format to enable a single, golden specification for low-power design intent to drive both the design and verification processes. <br /><br />“We’re happy to see both new tapeout successes for Ricoh and for the Cadence Low-Power Solution,” said Chi-Ping Hsu, senior vice president of research and development for the implementation group at Cadence. “By joining the Power Forward Initiative, Ricoh exemplifies the advancement of systems companies involvement in this important low-power ecosystem.”</div> <div class="ExternalClass17C6961220514F1BAF40FC46B9BD9961"><br /><b>About Cadence</b><br />Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at <a href="http://www.cadence.com/">www.cadence.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass9F68D924EC6947168487EF9568C3292D"> <div>Dean Solov<br />Cadence Design Systems, Inc.<br />408-944-7226<br /><a href="mailto:dsolov@cadence.com">dsolov@cadence.com</a></div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClassEA98E5C9242E4A9BA2DFC2A16EA1DF56">Cadence, the Cadence logo, Incisive, Conformal and Encounter are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.</div> </span></span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=81" width="1" height="1">newsLow powerRicoh2009 European PFI Summit Hosted in Cambridge, UKhttp://www.powerforward.org/home/news/archive/2009/05/18/174.aspxMon, 18 May 2009 00:29:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:174admin0<p>If you are interested in finding out more about the content of the event please send an email to <a href="mailto:powerforward@cadence.com?subject=2009%20European%20Summit%20Proceedings">info@powerforward.org</a>.</p> <p>On June 17, 2009, ARM and the member companies of the Power Forward Initiative (PFI) hosted a free power-aware Design Summit in Cambridge, UK. Engineers and managers from the UK low-power community attended. John Biggs from ARM gave the keynote address titled "Every Joule is Sacred" where he discussed ARM's emphasis on low power, some key low power dissipation trends, and some of the challenges to implement low power techniques. Steve Carson from Cadence gave the other keynote entitled."EDA in a Greening World" where he discussed what is meant by Green design and how Cadence is enabling Green Design automation. Other presentations at the event were as follows:</p> <ul> <li> <p><span style="font-size:10pt;font-family:Arial;">ARM Low Power Design Experiences - Stuart Riches, ARM</span></p> </li> <li> <p><span style="font-size:10pt;font-family:Arial;">Implementing a Complete Low Power Flow From Architecture to GDS2 - Michael O'Sullivan, Cadence </span></p> </li> <li> <p><span style="font-size:10pt;font-family:Arial;">Migration towards a CPF-integrated and Automated Low-Power Flow  - Flavio Cali, S3</span></p> </li> <li> <p><span style="font-size:10pt;font-family:Arial;">Low Power design principles for short range wireless IPs - Santosh Shivadatta, Mindtree</span></p> </li> <li> <p><span style="font-size:10pt;font-family:Arial;">Reducing the IP Integration Complexity in Low Power Design - John Longvill, Cadence </span></p> </li> </ul> <p>If you are interested in finding out more about the content of the event please send an email to <a href="mailto:powerforward@cadence.com?subject=2009%20European%20Summit%20Proceedings">info@powerforward.org</a>.</p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=174" width="1" height="1">newseventsPFI SummitARMSiS Joins Power Forward Initiative To Assist In Delivering Power-Efficient Computing Platformshttp://www.powerforward.org/home/news/archive/2009/03/11/sis-joins-power-forward-initiative-to-assist-in-delivering-power-efficient-computing-platforms.aspxWed, 11 Mar 2009 22:15:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:60jprice0<p><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"><b>Chipset Provider to Offer CPF-Based Low-Power Design Solutions</b><br /><br /><b>TAIPEI, Taiwan, 11 Mar 2009</b><br /><br /> <div class="ExternalClass48D74A4AFE40413BAFDB2D2C77396EA7">Chipset design company SiS said today that it has joined the Power Forward Initiative (PFI) and plans to offer a Common Power Format (CPF)-based design solution for its chipset, motherboard, reference design and systems customers. <br /><br />SiS uses the Cadence® Design Systems, Inc. (NASDAQ: CDNS) Low-Power Solution, the industry's leading and complete flow that integrates logic design, verification, and implementation technologies with the widely deployed Common Power Format. Using this comprehensive approach to low-power design, teams can improve productivity, reduce risk, and achieve superior tradeoff among timing, power, and area requirements. <br /><br />“As a chipset designer, SiS continuously dedicates itself to using innovative computing technologies to provide more efficiency and convenience to users of electronic systems,” said Nelson Lee, Marketing Director at SiS. “Our participation in the Power Forward Initiative will help us to serve our customers in need of more power-efficient computing platforms.” <br /><br />“Through its participation in the Power Forward Initiative, SiS hopes to accelerate its customers’ migration to more power-efficient design methodologies,” said Pankaj Mayor, group director of Business Enablement at Cadence. “We welcome SiS to the Power Forward Initiative where they can work with industry leaders to deliver high-quality, low-power solutions to customers.” </div> <div class="ExternalClassF4E9F5EE20B8446985B3BAB0853DB991"><br /><b>About Power Forward Initiative</b><br />The Power Forward Initiative, which has more than 30 member companies, is an industry initiative sponsored by Cadence Design Systems which has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely-deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a href="http://www.powerforward.org/" target="_blank">www.powerforward.org</a>. <br /><br /><b>About Silicon Integrated Systems Corp. (SiS)</b><br />Silicon Integrated Systems (SiS), founded in 1987, is a worldwide leader in the development of leading-edge core logic chipsets. Over the last 20 years, its products have been widely used in various applications such as Desktop PCs, notebook PCs, Embedded Systems, Wireless Communications, Servers, and Digital Entertainment Devices. For more information about SiS, please click <a href="http://www.sis.com/" target="_blank">www.sis.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass5B4B0725EB9C48A3BEFECAF5CBF9233F"> <div>Nelson Lee<br />Silicon Integrated Systems Corp.<br />886-2-8913-1168<br /><a href="mailto:nelson@sis.com">nelson@sis.com</a></div> <br /> <div>Dan Holden <br />Power Forward Initiative<br />1-408-944-7457 <br /><a href="mailto:holden@cadence.com">holden@cadence.com</a> </div> </div> </span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=60" width="1" height="1">newsSiSpartners LSI Joins Power Forward Initiativehttp://www.powerforward.org/home/news/archive/2008/11/17/lsi-joins-power-forward-initiative.aspxTue, 18 Nov 2008 12:18:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:61jprice0<p><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"><b>Common Power Format-enabled Low-Power Design Solutions to Enable Power-Efficient Electronics</b><br /><br /><b>San Jose CA, 17 Nov 2008</b><br /><br /> <div class="ExternalClassF25AB801E50944F88DEC86E045E739EE"><a href="http://www.powerforward.org/" target="_blank">Power Forward Initiative</a> (PFI) today announced that LSI (NYSE: LSI) has joined the initiative in order to collaborate with other industry leaders to advance the state-of-the-art in low-power design. PFI membership has grown to more than 35 companies from around the world who represent a broad spectrum of semiconductor, IP, EDA, ASIC, design services and manufacturing providers. <br /><br />"The energy footprint of storage and networking IC's must be reduced," said Ameesh Desai, senior director of design tools and methodology, LSI Corporation. "PFI's goal, which is to accelerate the delivery of low power IC's to the market, is in alignment with LSI Green initiatives. We look forward to contributing to this important effort." <br /><br />LSI offers a unique perspective on many of the low-power issues being addressed by the PFI. Working collaboratively with Cadence and other PFI members, LSI plans to accelerate delivery of low-power solutions to the market that leverages the Common Power Format (CPF). <br /><br />"The demand for power-efficient design is growing rapidly for wired applications driven by business and environmental considerations," said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. "By joining the Power Forward Initiative, LSI is affirming their commitment to collaborate with the industry to support customers' requirements to reduce energy consumption. We welcome their participation and applaud their leadership." </div> <div class="ExternalClass5657EB5C50E24BD29A8F759D6667788B"><br /><b>About LSI</b><br />LSI Corporation (NYSE: LSI) is a leading provider of innovative silicon, systems and software technologies that enable products which seamlessly bring people, information and digital content together. The company offers a broad portfolio of capabilities and services including custom and standard product ICs, adapters, systems and software that are trusted by the world’s best known brands to power leading solutions in the Storage and Networking markets. More information is available at <a href="http://www.lsi.com/" target="_blank">www.lsi.com</a>. <br /><br /><b>About Power Forward Initiative</b><br />The Power Forward Initiative, which has more than 35 member companies, is an industry initiative sponsored by Cadence Design Systems (NASDAQ: CDNS) and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. The Common Power Format (CPF) was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a href="http://www.powerforward.org/" target="_blank">www.powerforward.org</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass8B98BD99179140F7B45A0BE22C66CED3"> <div>Dan Holden <br />Power Forward Initiative<br />1-408-944-7457 <br /><a href="mailto:holden@cadence.com">holden@cadence.com</a> </div> </div> </span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=61" width="1" height="1">newsLSIpartnersPFI Hosts First Low-Power Summit in Silicon Valleyhttp://www.powerforward.org/home/news/archive/2008/10/13/139.aspxMon, 13 Oct 2008 00:02:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:139Power Forward0<p><span id="ctl00_ctl28_g_95884189_6740_4bcc_89c7_f92248842613_ctl00_output_content">"Over the past 2<sup>½</sup> years since the PFI was launched, membership has grown from 10 to 36 companies," explained Pankaj Mayor, Business Development Group Director at Cadence. "The PFI’s focus has shifted from developing CPF to the practical use of low-power design solutions and ecosystem building. This resonated well with attendees—85 percent of whom are already engaged in low-power design or will be within the next 6 months." <br /><br />Mayor opened the day-long conference and announced that LSI Corporation, Chartered Semiconductor, and SIS Taiwan have joined the Power Forward Initiative. He attributed the boom in low-power design adoption to the massive growth in global energy consumption due to electronics, especially Internet applications such as online gaming and search engines. <br /><br /><b>NVIDIA saves power</b> <br />The morning keynote by Chris Malachowsky, an NVIDIA founder, set the stage for further discussions on low power. "When you begin your design you have to ask yourself what is the lowest power you can operate at for the job you're trying to do? You have to take a holistic view of your design." <br /><br /><img src="http://www.cadence.com/_layouts/images/imgbin/AboutCadence/features/img_panel1a.jpg" align="right" alt="" /> Malachowsky said NVIDIA has three ways of looking at low-power designs: One is when building something for the absolute lowest power in portable devices, two is performance that is dictated in a PC chassis, and three is designing at the highest end to get the highest performance in a power budget. <br /><br />Many power saving methods have also been applied to their flagship video processors, Malachowsky said. "We have aggressive clock gating, aggressive enabling and disabling, like active termination, clock frequency, power VDV levels, etc. We have seen a 2-3x improvements in our performance per watt." <br /><br /><b>Technical Sessions</b> <br />PFI member companies AMD, ARM/UMC, Faraday, and Freescale highlighted examples of successful low-power design projects ranging from power-efficient GPU design to ARM CPU methodologies to automotive low-power design considerations. David Lan of TSMC, a founding member of PFI, highlighted how industry collaboration to integrate process technology advancements with new design techniques is critical to producing energy-efficient chips and delivering real value to mutual customers. <br /><br />The collaboration message was echoed by other PFI members, who highlighted the broad support by IP companies in the ecosystem for CPF-based low-power design methodologies. Presentations by ARM, ARC, Chartered Semiconductor, Virage Logic, and Sonics reviewed products and methodologies available today that build power-efficient chips. <br /><br />The hot topic for many at the summit was architectural low-power tradeoff techniques. A standing-room-only crowd enjoyed presentations from Cadence featuring low-power chip planning and how quickly C-to-Silicon Compiler helped Broadcom analyze various architectures to optimize tradeoffs among power and performance criteria. Calypto presented novel techniques for architectural optimization, and Sequence discussed RTL power prototyping. <br /><br /><b>Deployment Challenges</b> <br />PFI Coordinator Susan Runowicz-Smith moderated a panel discussing the challenges to mainstream low-power design adoption. Seasoned low-power experts from NXP, Freescale, LSI, and Virage Logic populated the panel. The most telling of all attendee comments after the presentation was: "Low-power design complicates design flows, but the payoff is big.” <br /><br /><b>Going Green</b> <br />Wrapping up the day, Carl Guardino, CEO of the Silicon Valley Leadership Group, stressed that "going green" is not just going to save the planet, but is in the best interest of companies in Silicon Valley, which can become the epicenter for burgeoning green industries. He noted that data centers, power-use hubs for the Internet, <img style="margin-top:10px;" src="http://www.cadence.com/_layouts/images/imgbin/AboutCadence/features/img_lastpanel.jpg" align="left" alt="" />will continue to consume more power unless the semiconductor industry comes together to find solutions. "By 2011, at current growth rates, they will consume enough power to require ten new power plants in the U.S. alone." <br /><br />A panel led by Ron Wilson, EDN Executive Editor, expanded on the practical side of the low-power design equation to include techniques people are using to save power at home. <br /><br />"The meeting exceeded expectations–in terms of presentations and attendance," concluded Pankaj Mayor. "Energy efficiency is an important global initiative and Cadence is playing a leading role in enabling green electronics." </span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=139" width="1" height="1">PFI SummitTensilica Collaborates with Cadence to Create CPF-Enabled Flow for Tensilica’s Multimedia Subsystemshttp://www.powerforward.org/home/news/archive/2008/09/10/tensilica-collaborates-with-cadence-to-create-cpf-enabled-flow-for-tensilica-s-multimedia-subsystems.aspxThu, 11 Sep 2008 00:23:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:63jprice0<div id="NewsPostDetailContent"> <p><b>SANTA CLARA, Calif. – September 9, 2008 </b>– Tensilica, Inc. announced today that they have collaborated with Cadence (NASDAQ: CDNS) to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi Audio Processor and 388VDO Video Engine. Cadence and Tensilica engineers worked together to develop an implementation of the Tensilica multiprocessor audio-video platform using the complete Cadence Low-Power Solution including Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter RTL-to-GDSII system.</p> <p>The 388VDO Video Engine is a fully programmable codec processor that supports multi-standard, multi-resolution video. Both are targeted at mobile handsets and personal media players (PMPs). Now, SoC designers can now build upon the Tensilica reference design by employing the Cadence Low-Power Solution to deliver the lowest-power implementation for power-sensitive mobile applications.</p> <p>"The combination of Tensilica IP with the Cadence Low-Power Solution equips customers with all the tools and technology they need to create power-efficient, portable multimedia chips," stated Chris Jones, Tensilica’s director of strategic alliances. "By using this reference flow based on the widely deployed Common Power Format, our customers will be able to save precious design time while employing the most advanced techniques for low-power design."</p> <p>"Tensilica has been an active participant in the Power Forward Initiative which has the goal of enabling the design and production of more power-efficient electronic devices," said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. "This proof point project demonstrates that by using CPF with the Tensilica processor and the Cadence Low-Power Solution, multimedia chip designers can accelerate delivery of ultra-low-power products to their markets."</p> <p>For 330HiFi and 388VDO users, Tensilica will deliver example reference scripts for Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter RTL-to-GDSII system, along with example CPF files describing power intent for the 388VDO processor. The CPF package will be available in the fourth quarter of 2008.</p> <h3><span class="style1">About Tensilica</span></h3> <p>Tensilica, Inc., is the recognized leader in customizable applications processors, DSPs and standard IP cores for audio, video, imaging, security, networking, and baseband signal processing. The automated design tools behind all of Tensilica’s customizable applications processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones, consumer electronics devices (including portable media players, digital TV, and broadband set top boxes), computers, and storage, networking and communications equipment. For more information on Tensilica’s patented, benchmark-proven processors, visit <a href="http://www.tensilica.com/" target="_self">www.tensilica.com</a>.</p> <p align="center"># # #</p> <h3>Editors’ Notes:</h3> <ul> <li class="smalltext">Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names mentioned are trademarks and/or registered trademarks of their respective owners. </li> <li class="smalltext">Tensilica’s announced licensees include: ADDMM, Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Berkeley Wireless Research Center, Brocade, Broadcom, Cisco Systems, CMC Microsystems, Conexant Systems, Design Art Networks, DS2, EE Solutions, Epson, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, iBiquity Digital, Ikanos Communications, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Penstar, Plato Networks, PnpNetwork Technologies, SiBEAM, Silicon Optix, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, Triductor Technology, u-Nav Microelectronics, UpZide, Valens Semiconductor, Validity Sensors, Victor Company of Japan (JVC), WiLinx, WiQuest Communications, and XM Radio</li> </ul> </div><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=63" width="1" height="1">newsTensilicapartnersWipro Technologies Joins Power Forward Initiativehttp://www.powerforward.org/home/news/archive/2008/09/08/106.aspxMon, 08 Sep 2008 01:54:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:106Power Forward0<p><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"><b>CPF-enabled Low-Power Design Solution to Enable Energy Efficient Electronics</b><br /><br /><b>San Jose CA, 08 Sep 2008</b><br /><br /> <div class="ExternalClass7B2CB4CD76074073A5B276F3C8C828D5"><a href="http://www.powerforward.org/" target="_blank">Power Forward Initiative</a> (PFI) today announced that Wipro Technologies has recently joined the initiative and is offering Common Power Format (CPF)-enabled low-power design capabilities to its design services customers worldwide. The PFI membership has now grown to over 30 companies around the world, representing a broad spectrum of semiconductor, IP, EDA, ASIC, design services and manufacturing providers. <br /><br />Wipro has adopted the Cadence® Design Systems, Inc. (NASDAQ: CDNS) Low-Power Solution, which integrates leading-edge design, verification, and implementation technology with the widely deployed CPF standard to deliver an end-to-end low-power design solution to IC engineers. By preserving low-power design intent throughout the design process, the solution eliminates laborious manual work, reduces power-related chip failure, and provides power predictability early in the design process, enabling sharing and reuse of low-power intelligence throughout the design process. <br /><br />Wipro is the largest independent provider of R&D services in the world. Using an “Extended Engineering” model for leveraging R&D investment and accessing new knowledge and experience across the globe, people and technical infrastructure, Wipro enables firms to introduce new products rapidly. Using the Cadence Low-Power Solution will enable Wipro’s delivery of more power efficient chip designs. <br /><br />"Reducing the energy footprint of electronic products has become an important consideration for ICs and subsystems targeting a wide range of both handheld and wired products," said Vasudevan Aghoramoorthy, vice president, Semiconductor & System Solutions, Wipro Technologies. "Cadence's commitment to driving industry-wide solutions in low power design is in direct alignment with Wipro's own low power design Green initiatives. We are pleased to join Cadence and other industry leaders in this important effort." <br /><br />"The demand for low power design is growing rapidly in all geographies driven by business and environmental considerations," said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. "By joining the Power Forward Initiative, Wipro is affirming their commitment to collaborate with the industry to support customers’ mandates to reduce energy consumption." </div> <div class="ExternalClassB7CB8C33CC614D6CBE2E9D0FD0E5C1CE"><br /><b>About Power Forward Initiative</b> <br />The Power Forward Initiative, which has more than 30 member companies, is an industry initiative sponsored by Cadence Design Systems and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a href="http://www.powerforward.org/" target="_blank">www.powerforward.org</a>. <br /><br /><b>About Wipro</b> <br />Wipro (NYSE:WIT) is a $4 bn global provider of IT Services, Outsourced R&D, Infrastructure Outsourcing, Business Process Services, and Business Consulting. With 25 years in the global delivery of technology services, Wipro is the world’s largest third-party provider of R&D services and the world’s first PCMM and CMMi level company. Rated by industry analysts as a leader in global package implementation projects, CRM services, and Infrastructure Management among offshore firms, Wipro has won global recognition and awards for innovation and outsourcing excellence. <br /><br />Wipro Technologies’ 2100+ Semiconductor / System engineers and 16,000+ embedded software engineers make it the World’s largest independent R&D service provider. Combined with best-in-class methodology, EagleWision™ Wipro has one of the best first-pass-success rate for 300+ silicon and 200+ system designs delivered over the last 2 years. These include engagements in 65nm, 90nm and 0.13µ for telecommunication, storage, avionics, consumer electronics, medical electronics, automotive and industrial control domains. For more information, please visit our websites at <a href="http://www.wipro.com/" target="_blank">www.wipro.com</a>, <a href="http://www.wiprocorporate.com/" target="_blank">www.wiprocorporate.com</a>, <a href="http://www.wipro.com/vlsi" target="_blank">www.wipro.com/vlsi</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClassFC26EC4274C74FA8B29021AF5F5222B4"> <div>Dan Holden<br />Power Forward Initiative <br />408-944-7457<br /><a href="mailto:holden@cadence.com">holden@cadence.com</a></div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClassEDEFCE6A1099465D8240B7B263FAFD20">Cadence is a registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.</div> </span></span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=106" width="1" height="1">newsWiPropartnersSonics Joins Power Forward Initiativehttp://www.powerforward.org/home/news/archive/2008/09/03/sonics-joins-power-forward-initiative.aspxThu, 04 Sep 2008 11:26:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:64jprice0<p class="MsoNormal" style="text-align:center;" align="center"><span style="font-size:small;"><i>Sonics to Present Low-Power Collaboration Results at CDNLive Silicon Valley</i></span></p> <p class="MsoNormal" style="line-height:150%;"><span style="font-size:small;"> </span><b><br />Milpitas, Calif</b>. – <b>Sept. 3, 2008</b> - Sonics Inc., a premier supplier of system-on-chip (SoC) SMART Interconnect™ solutions<span>, </span>today announced that as part of its commitment to power management solutions, it has joined the Power Forward Initiative.<span> </span>Sonics is committed to integrated, industry-wide solutions for low-power design and providing a platform for higher-level exploration and IP reuse.<span> </span>Through the Power Forward Initiative, Sonics will work with a collective of leading technology companies addressing power efficiency across the electronics ecosystem.</p> <p class="MsoNormal" style="line-height:150%;">Currently, advanced SoCs targeting both wireless and wireline applications are experiencing power challenges that require power management solutions spanning the full range from system and architectural design through logical and physical implementation.<span> </span>Coordination among these solutions and across the functional subsystems on the SoC is needed to deliver the required power savings. For this reason, linking architectural power management with implementation-level power management is becoming an important requirement to realize overall power savings.</p> <p class="MsoNormal" style="line-height:150%;">“Sonics has a vision of enabling designers to efficiently manage power consumption by seamlessly linking power domain architectures and the associated controllers to the physical implementation domain,” said Benoit de Lescure, application engineer and power management expert, Sonics Inc. “We have adopted the Common Power Format (CPF) as a mechanism to connect our architecture-level, low-power initiative with the chip design and manufacturing solutions from Cadence. By combining power-sensitive interconnects with power-aware design verification and implementation methodology, SoC developers can expect seamless power management through the entire process from architecture concept to silicon.”</p> <p class="MsoNormal" style="line-height:150%;">Sonics SMART Interconnect solutions combine aggressive fine grain clock gating to minimize active power with coarse grain gating to minimize idle power, resulting in the industry’s lowest power interconnect solutions.<span> </span>In addition, Sonics solutions include power management services that enable SoCs to cleanly control power state transitions including stopping clocks and/or switching off local supply voltages without risk of losing transactions or corrupting system states.</p> <p class="MsoNormal" style="line-height:150%;">“Low power IP is critical in enabling power-efficient electronics,” said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc.<span> </span>“We welcome Sonics to the Power Forward Initiative and look forward to incorporating their architectural perspective into the group.<span> </span>Working collaboratively, Sonics and other industry leaders in the Power Forward Initiative will enable customers to achieve their low-power goals.” </p> <p class="MsoNormal" style="line-height:150%;">Sonics Director of Software Development, Scott Evans and Cadence Architect for IC Verification, Neyaz Khan will co-present a paper titled “<span>CPF Flow for Highly-Configurable Interconnect IP”</span> at this year’s CDNLive on September 9.<span> </span>This informative talk is part of CDN Live Track Two, Functional Verification B, at 2:15-3pm at the San Jose Convention Center. For more information about this event, please go to www.cadence.com/cdnlive.<span></span></p> <p class="MsoNormal" style="line-height:150%;"><b>About Power Forward Initiative</b> <br /> The Power Forward Initiative, which has more than 30 member companies, is an industry initiative sponsored by Cadence Design Systems and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross-section of the design chain, including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely-deployed low-power intent standard in the industry and available from Si2. The Initiative has also published <i>A Practical Guide to Low-Power Design – User experience with CPF </i>which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a href="http://www.powerforward.org/">www.powerforward.org</a>. </p> <p class="MsoNormal" style="line-height:150%;"><b>About Sonics</b><b><span></span></b><br />Sonics Inc. is a premier supplier of SMART Interconnect solutions, delivering high SoC design predictability and increased design efficiency. Its solutions address the growing complexity found in consumer products with voice, data and video features.<span> </span>Major semiconductor and systems companies including Broadcom, Samsung, Texas Instruments and Toshiba leverage Sonics’ technology in leading products in the wireless, digital multimedia and communications markets.<span> </span>For more information, see <a href="http://www.sonicsinc.com/">www.sonicsinc.com</a>. </p> <p class="MsoNormal" style="text-align:center;line-height:150%;" align="center"><b>#<span> </span>#<span> </span>#</b></p> <p> <span>®</span><span style="font-size:10pt;color:black;">Sonics Inc., the company's logo and SMART Interconnect are registered trademarks of Sonics Inc.<span> </span>All other trademarks are the property of their respective owners.</span><span style="font-size:10pt;font-family:Palatino;color:black;"><br /> <br /> </span><b>Media Contacts:</b><br /><span style="font-size:10pt;">Mary Jane Reiter</span><span style="font-size:10pt;"><br />Fast Forward Public Relations<br />408-725-1239<br /><a href="mailto:mjreiter@sbcglobal.net">mjreiter@sbcglobal.net</a></span></p><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=64" width="1" height="1">newsSonicsSandLinks Achieves First-Time Right Silicon Using CPF-Enabled Cadence Low-Power Solutionhttp://www.powerforward.org/home/news/archive/2008/08/25/82.aspxMon, 25 Aug 2008 09:58:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:82Power Forward0<table id="CadenceProduct_MainTable" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;" cellpadding="0" cellspacing="0"> <tbody> <tr id="TopRow"> <td id="TopCell"> <div style="padding-right:1px;padding-left:1px;"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td id="MSOZoneCell_WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td> <div id="WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621" class="ms-WPBody"> <div id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"> <div id="body_text" style="padding-left:15px;padding-right:15px;"><b>Design Flow Helps Developer of Next Generation Active-RFID Networks Achieve Longer Battery Life for Active RFID Tags</b><br /><br /><b>HERZELIA, Israel, 25 Aug 2008</b><br /><br /> <div class="ExternalClassCB605B358FF942A187ECA64F8E4FA04D">Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that SandLinks, Inc., has received functional silicon of its low-power RFID tag device which was implemented using the Common Power Format (CPF)-enabled Cadence® Low-Power Solution. SandLinks was able to achieve key requirements for this chip, including ultra-low-power consumption and longer battery life for the active RFID tag. <br /><br />SandLinks used the complete Cadence Low-Power Solution, including Encounter® RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter® RTL-to-GDSII system. For the design and implementation of the radio part of its UWB transceiver, SandLinks used the Cadence Virtuoso® custom design platform. <br /><br />“Using CPF, our engineers described the power intent as part of the RTL delivery to the back-end design house, shortening the loops, providing consistent guidance and avoiding misunderstanding between the front-end and back-end engineers,” said <br /><br />Dr. Gideon Kaplan, SandLinks co-founder and vice president of research and development. “The proof of the flow is our successful silicon. We estimate that we were able to save about 10 weeks of precious design time by using Cadence's CPF-based low-power design flow.” <br /><br />Encounter RTL compiler global synthesis was employed to predict and optimize power consumption. During verification, SandLinks used CPF, allowing the designers to verify, among other things, the on-off functionality of the chip. The tapeout was on time, and silicon results demonstrated the functionality of SandLinks’ UWB transceiver, enabling the company to go ahead with the testing and marketing of its novel RFID system. <br /><br />“This design provides yet another perfect example of the value of the Cadence Low-Power Solution - first-time right silicon on time,” said Dr. Chi-Ping Hsu, Cadence corporate vice president, IC Digital and Power Forward. “The Cadence Low-Power Solution has been production proven and used successfully in production at more than 50 companies. The low-power design methodology, with the Si2 Common Power Format as a basis, enables these companies to quickly deliver highly competitive ultra-low-power products to their markets.” <br /><br />To help design teams adopt advanced power-management techniques, Cadence developed the industry’s first complete solution for the design, verification, and implementation of low-power chips. The Cadence Low-Power Solution combines a variety of Cadence technologies that leverage the Si2 Common Power Format, which specifies power-saving techniques early in the design process—enabling design teams to share and reuse low-power intelligence. </div> <div class="ExternalClass8610A31216DC4A418169974907B204FD"><br /><b>About Cadence</b><br />Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at <a href="http://www.cadence.com/">www.cadence.com</a>. </div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClass3E37ADB73B4A4611BFDB95480D232995"> <div>Andrea Huse<br />Cadence Design Systems, Inc.<br /><a href="mailto:ahuse@cadence.com">ahuse@cadence.com</a><br />498945631726</div> </div> <br /><br /><span class="press_footer"> <div class="ExternalClassFC2359DEFB174D139511A1B7B0A58866"> <div>Cadence, Virtuoso, and Encounter are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.</div> </div> </span></div> </span> </div> </div> </td> </tr> </tbody> </table> </td> </tr> </tbody> </table> <div class="topbanner" id="Zone_Template_1_image_area"> </div> </div> </td> </tr> <tr id="MiddleRow"> <td id="CadenceProdSoluMainContent" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;"> </td> </tr> </tbody> </table><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=82" width="1" height="1">newsLow-powerSandLinksPower Forward Initiative Momentum Continues with Addition of Three Leading Japanese Design Services Companieshttp://www.powerforward.org/home/news/archive/2008/07/08/108.aspxTue, 08 Jul 2008 18:02:00 GMT2151c306-1704-4d62-833d-93f0cfd9f992:108Power Forward0<table id="CadenceProduct_MainTable" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;" cellpadding="0" cellspacing="0"> <tbody> <tr id="TopRow"> <td id="TopCell"> <div style="padding-right:1px;padding-left:1px;"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td id="MSOZoneCell_WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"> <table cellpadding="0" cellspacing="0"> <tbody> <tr> <td> <div id="WebPartctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621" class="ms-WPBody"> <div id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621"><span id="ctl00_ctl28_g_8b6bcb0f_c7b7_4d0e_8c5a_36cd4cc0a621_ctl00_output_content"> <div id="body_text" style="padding-left:15px;padding-right:15px;"><b>NIPPON SYSTEMWARE Co., Ltd., DNP Co., Ltd. and Toppan Technical Design Center Co., Ltd. Provide Capabilities for Faster, More Accurate Low-Power Design</b><br /><br /><b>San Jose, Calif., 09 Jul 2008</b><br /><br /> <div class="ExternalClass680CF48919864A11A6FB94045A50757C"> <p> The <a href="http://www.powerforward.org/">Power Forward Initiative</a> (PFI) today announced that three Japanese design services companies recently joined the initiative and are offering Common Power Format (CPF)-enabled low-power design capabilities to their design services customers. With the addition of these three leading Japanese design centers — NIPPON SYSTEMWARE CO., LTD. (NSW), Dai Nippon Printing Co., Ltd. (DNP) and Toppan Technical Design Center Co., Ltd. — the PFI increases its membership to over 30 companies around the world, representing a broad spectrum of IC design, IP, service and manufacturing providers. </p> <p> All three design services companies have adopted the Cadence® Design Systems, Inc. (NASDAQ: CDNS) Low-Power Solution, which integrates leading-edge design, verification and implementation technology with the widely deployed CPF standard to deliver an end-to-end low-power design solution to IC engineers. By preserving low-power design intent throughout the design process, the solution eliminates laborious manual work, reduces power-related chip failure, and provides power predictability early in the design process, enabling sharing and reuse of low-power intelligence throughout the design process. </p> <p> NSW is an independent IT company and a leading provider of embedded total solutions in the LSI design service market. NSW assists customers designing ICs for graphics, communication/network, mechanical control applications and ARM-embedded SoCs as an ARM-approved design center. </p> <p> "Low-power design is considered ecologically friendly, and is therefore becoming a key requirement for designers of ICs targeting consumer products," said Seiichi Koseki, associate general manager, System Logic Technology division of NSW. "By using the Common Power Format for low-power hand-off, we can deliver low-power designs to our customers faster and meet their requirements more consistently." </p> <p> DNP provides LSI design services for a variety of applications, including microprocessors for consumer electronics, ASICs and SoCs, mixed-signal, memory, CCD and CMOS image sensors, display drivers, and power supplies through its subsidiary for LSI design service, DNP LSI Design Co., Ltd. </p> <p> "The Common Power Format will allow our design teams to increase designer productivity and reduce energy consumption which is valuable to our customers," said Yasuo Jimbo, general manager of LSI Design & Development Department, 1st Sales Division, Electronic Device Operations at DNP. "Through our design consulting services, we have experienced the value of CPF-based low-power design." </p> <p> Toppan Technical Design Center provides custom, multipurpose services, including systems design, logic design, and chip-level and IP integration using C-level or HDL design as well as chip-level layout. Toppan also provides capabilities and superior technologies for ARM-based design as an ARM-approved design center, as well as analog RF and power supply design. </p> <p> "A large number of new designs are for communications and consumer products requiring low-power implementations," said Takashi Nabuchi, manager, Asaka design center of Toppan Technical Design Center. "CPF provides the mechanism for communicating low-power intent that helps us give our customers exactly what they want." </p> <p> "Low-power design is a significant and growing trend in the Japan semiconductor market, where an increasing percentage of design work is targeted to consumer applications," said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. "By joining the Power Forward Initiative, NSW, DNP and Toppan can bring additional value to their customer engagements both in terms of low-power design capabilities, and in support of their customers' programs to reduce energy consumption. We applaud their leadership." </p> </div> <div class="ExternalClassB85FF85328CD41E8BC1099C362EB662C"><b>About Power Forward Initiative</b><br /> The Power Forward Initiative, which has more than 30 member companies, is an industry initiative sponsored by Cadence Design Systems and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design — User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at <a href="http://www.powerforward.org/">www.powerforward.org</a>.</div> <br /><b>For more information, please contact:</b><br /> <div class="ExternalClassC57CC9A0B31546389C73E9989B19D7F3">Dan Holden<br />Direct:+1 408.944.7457<br /><a href="mailto:holden@cadence.com">holden@cadence.com</a><br />Power Forward Initiative<br /></div> <br /><br /><span class="press_footer"> <div class="ExternalClassF54E292F62D6429A8CE9E8ACEB19B0A9">Cadence is a registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners</div> </span></div> </span> </div> </div> </td> </tr> </tbody> </table> </td> </tr> </tbody> </table> <div class="topbanner" id="Zone_Template_1_image_area"> </div> </div> </td> </tr> <tr id="MiddleRow"> <td id="CadenceProdSoluMainContent" style="background:transparent url(/_layouts/images/imgbin/rounded_corners/white_bg_bars.gif) repeat scroll 0% 0%;width:635px;"> </td> </tr> </tbody> </table><div style="clear:both;"></div><img src="http://www.powerforward.org/aggbug.aspx?PostID=108" width="1" height="1">newsDNPToppanNippon