Chipset design company SiS said today that it has joined the Power Forward Initiative (PFI) and plans to offer a Common Power Format (CPF)-based design solution for its chipset, motherboard, reference design and systems customers.

SiS uses the Cadence® Design Systems, Inc. (NASDAQ: CDNS) Low-Power Solution, the industry's leading and complete flow that integrates logic design, verification, and implementation technologies with the widely deployed Common Power Format. Using this comprehensive approach to low-power design, teams can improve productivity, reduce risk, and achieve superior tradeoff among timing, power, and area requirements.

“As a chipset designer, SiS continuously dedicates itself to using innovative computing technologies to provide more efficiency and convenience to users of electronic systems,” said Nelson Lee, Marketing Director at SiS. “Our participation in the Power Forward Initiative will help us to serve our customers in need of more power-efficient computing platforms.”

“Through its participation in the Power Forward Initiative, SiS hopes to accelerate its customers’ migration to more power-efficient design methodologies,” said Pankaj Mayor, group director of Business Enablement at Cadence. “We welcome SiS to the Power Forward Initiative where they can work with industry leaders to deliver high-quality, low-power solutions to customers.”