Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that SandLinks, Inc., has received functional silicon of its low-power RFID tag device which was implemented using the Common Power Format (CPF)-enabled Cadence® Low-Power Solution. SandLinks was able to achieve key requirements for this chip, including ultra-low-power consumption and longer battery life for the active RFID tag.

SandLinks used the complete Cadence Low-Power Solution, including Encounter® RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter® RTL-to-GDSII system. For the design and implementation of the radio part of its UWB transceiver, SandLinks used the Cadence Virtuoso® custom design platform.

“Using CPF, our engineers described the power intent as part of the RTL delivery to the back-end design house, shortening the loops, providing consistent guidance and avoiding misunderstanding between the front-end and back-end engineers,” said

Dr. Gideon Kaplan, SandLinks co-founder and vice president of research and development. “The proof of the flow is our successful silicon. We estimate that we were able to save about 10 weeks of precious design time by using Cadence's CPF-based low-power design flow.”

Encounter RTL compiler global synthesis was employed to predict and optimize power consumption. During verification, SandLinks used CPF, allowing the designers to verify, among other things, the on-off functionality of the chip. The tapeout was on time, and silicon results demonstrated the functionality of SandLinks’ UWB transceiver, enabling the company to go ahead with the testing and marketing of its novel RFID system.

“This design provides yet another perfect example of the value of the Cadence Low-Power Solution - first-time right silicon on time,” said Dr. Chi-Ping Hsu, Cadence corporate vice president, IC Digital and Power Forward. “The Cadence Low-Power Solution has been production proven and used successfully in production at more than 50 companies. The low-power design methodology, with the Si2 Common Power Format as a basis, enables these companies to quickly deliver highly competitive ultra-low-power products to their markets.”

To help design teams adopt advanced power-management techniques, Cadence developed the industry’s first complete solution for the design, verification, and implementation of low-power chips. The Cadence Low-Power Solution combines a variety of Cadence technologies that leverage the Si2 Common Power Format, which specifies power-saving techniques early in the design process—enabling design teams to share and reuse low-power intelligence.