Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the 45-nanometer reference flow targeting Common Platform™ technology available for general release in July 2008. Cadence® and the Common Platform technology companies, comprised of IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, collaborated to develop this RTL to GDSII 45-nanometer flow to address advanced node design requirements. This reference flow is based on the Common Power Format (CPF)-enabled Cadence Low-Power Solution and also includes key Design For Manufacturing (DFM) technology from Cadence. This joint optimization is expected to provide significant power savings, yield enhancement and time-to-market advantages for customers designing high-volume consumer, communications and mobile electronic devices targeted to the Common Platform technology 45-nanometer process.

This reference flow uses the 45-nanometer ARM® Physical IP low-power libraries and enables designers to perform design exploration and physical prototyping using different CPF files and a single golden RTL, allowing low-power architecture optimization. It employs the advanced power management capabilities in the Cadence Low-Power Solution — including power shut off prototyping, power domain-aware placement, clock tree synthesis and routing, multi-mode and multi-corner analysis and optimization — to deliver higher productivity and the utmost in power reduction for advanced designs.

"Consumer demand for portable products is accelerating as longer, reliable connectivity becomes a necessity. This is driving an increasing demand for designs with optimized power management schemes," said Tom Lantzsch, vice president of marketing, Physical IP Division at ARM. "Working with Cadence, ARM is aggressively pursuing the enablement of our mutual customers to develop industry leading embedded products. As part of this collaboration, we are now offering CPF views with the ARM Physical IP libraries. The 45-nm ARM Physical IP with Power Management Kit targeted to the Common Platform technology is the latest evolution of our commitment to CPF-based reference flow collaboration with Cadence."

As part of this 45-nm reference flow, Cadence also provides an integrated suite of foundry certified, model-based DFM analysis and implementation technologies for silicon-accurate analysis and physical design optimization. These technologies offer silicon-accurate modeling and optimization of critical manufacturing variations that can be used to improve both performance and physical yield results during design implementation. At advanced process nodes, traditional design flows no longer provide accurate predictability, forcing designers to either guardband their designs excessively or risk manufacturability problems. By modeling key manufacturing processes within the implementation flow and optimizing early, designers reduce overall turnaround time and improve their confidence that the chip will work as intended.

This 45-nm reference flow is built around the Cadence Encounter® platform for DFM-aware prevention, detection and optimization. It has been demonstrated within the Common Platform that features which may result in yield-limiting issues in lithography are quickly and accurately identified using the Cadence Litho Physical Analyzer. These model-based DFM results are used to drive the Cadence SoC Encounter™ RTL-to-GDSII system — for prevention and manufacturing-aware design closure, and Cadence Chip Optimizer - for incremental space-based interconnect optimization and final manufacturability optimization. Cadence QRC Extractor provides the essential modeling link between the physical, manufacturing and electrical domains. DFM effects can be extracted and timing impact can be back-annotated to the physical implementation stage for accurate model-based timing optimization.

The Cadence 45nm reference flow for the Common Platform, provides capabilities which help bring manufacturing predictability back to the designer. This drives result in higher quality silicon with better time-to-volume.

"Low-power design and design for manufacturability are key factors for customers when choosing to adopt the 45-nm Common Platform technology," said Mark Ireland, vice president, Common Platform, at IBM. "In order to address these issues, the Common Platform companies worked with Cadence engineers to deliver this 45-nm reference flow. The result is an innovative yield-aware solution with seamless implementation of power intent using CPF."

"This collaboration between Cadence and the Common Platform provides a 45-nm silicon-aware reference flow that can be quickly deployed by engineering teams seeking predictable design flows that deliver superior quality of silicon," said Chi-Ping Hsu, corporate vice president of Digital IC and Power Forward at Cadence. "The combination of the Cadence Low-Power Solution and DFM technologies, and the Common Platform 45-nm process technology, provide designers a complete solution to address the complexities and interdependent needs of low power and advanced process technology."

The Advanced node capabilities in the Cadence 45nm Reference Flow provide "what you design is what you get" (WYDIWYG) modeling, advanced low power techniques, and optimization of critical manufacturing variations that can be used to improve results of the design phase. This helps to result in faster, lower power and more accurate silicon.

Availability
The 45-nanometer advanced low-power, yield-optimization reference flow will be available in July by sending an email request to common_platform_45LP@cadence.com. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.