CPF-Based Faraday SoCompiler Design Services leverages the Cadence Low-Power Solution
to achieve> 99% leakage reduction and 65% dynamic power reduction and significantly reduced design time
Faraday Technology Corporation (TAIEX: 3035), a leading ASIC and
silicon IP provider, and NemoChips, an emerging leader in low power
multimedia platform ICs, today announced that NemoChips has
successfully taped out a low-power mobile video platform SoC leveraging
Faraday's SoCompiler Design Services employing the Common Power Format
(CPF)-enabled Cadence® (NASDAQ: CDNS) Low-Power Solution. This
leading-edge design took only 2 months from netlist to tape-out while
achieving an impressive >99% leakage reduction and 65% dynamic power
reduction using advanced techniques such as Dynamic Voltage &
Frequency Scaling, Multi-Supply Voltages, and Power-Shut Off. ASIC
customers designing complex and power sensitive SoCs can benefit from
this proven methodology to dramatically reduce time to market as well
as to reduce implementation risk.
power, high performance, multimedia application processor is targeted
for use within mobile terminals, including mobile handsets, portable
media players, portable navigation devices and car entertainment
systems. It delivers DVD quality video to mobile devices without video
"We are pleased with the
performance, power savings and rapid tape-out of our mobile application
processor chip, which provides desktop-like multimedia experience to
our customer on handheld devices without sacrificing battery life."
said Dr. Lifeng Zhao, President of NemoChips Inc. "Faraday has clearly
demonstrated strong expertise in implementing complex low-power chips."
Faraday's SoCompiler Design Services team used the
Si2 standard Common Power Format to specify power-saving techniques
early, so the information could be reused throughout the design
process. The Cadence Low-Power Solution integrates logic design,
verification, and implementation with CPF, automating power-saving
design techniques like dynamic voltage and frequency scaling (DVFS)
without impacting delivery schedules.
early stages of the DVFS design, Faraday used Cadence Conformal LP,
Logic Equivalence Checker (LEC), and Faraday's internal design kit, to
handle best-in-class verification for this complex low power design.
The verification includes more than 30 automatic checking procedures in
the design flow, and it can be automatically performed in a few
minutes. Cadence Conformal Low Power technologies are highly
complementary and help Faraday to extend its ability to provide low
power technology to design bigger, faster chips.
has always committed to providing the most competitive solution to our
customers, and the Faraday PowerSmart™ design flow is a natural
extension of that commitment," said Dr George Hwang, VP of
International Business of Faraday Technology. "By working with Power
Forward Initiative members Cadence and UMC, we are able to help
Nemochips meet a set of stringent power requirements using a solution
that provided a 2x productivity improvement, enabling delivery within a
very short design cycle."
low-risk delivery of a low-power mobile platform to NemoChips
demonstrates the value of a highly automated and holistic low-power
solution," said Dr. Chi-Ping Hsu, corporate vice president, IC Digital
and Power Forward at Cadence. "We're excited about the continuing
silicon successes of CPF-based Cadence Low Power Solution. And we're
grateful for Faraday's recent contribution to "A Practical Guide to
Low-Power Design - User experience with CPF," which is an online guide
to low power design based entirely on actual user experience."
Practical Guide to Low-Power Design - User experience with CPF," is
published online by the Power Forward Initiative and available free of
charge at www.powerforward.org. In its chapter, Faraday provides
valuable insight into the methodologies used by the Faraday SoCompiler
Design Services team to make the NemoChips project a success.
05-27-2008 5:40 PM