Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex™-A9 processor. The flows are available for three configurations of the ARM Cortex-A9 processor: single core, dual Cortex-A9 MPCore™ multicore processor and quad Cortex-A9 MPCore™ multicore processor. Proven to enable ARM Cortex-A9 processor performance of up to 800MHz (production-margined at worst case PVT conditions), these reference methodologies offer time-to-market savings for customers designing for high performance within tight power constraints for next-generation devices such as smart phones, mobile internet devices, consumer electronics, automotive infotainment, networking and other embedded and enterprise devices.

ARM and Cadence jointly developed and tested these silicon-ready reference methodologies using ARM Artisan® physical IP targeted at a 65-nanometer process. These reference methodologies use the entire Encounter design flow from synthesis, test, and formal verification, to physical implementation and final sign-off, including concurrent static and dynamic power reduction and manufacturing-aware, rule-and-model-based yield optimization.

The reference methodologies represent what engineers can expect while doing actual tapeouts, including the necessary steps for silicon-ready design, such as timing analysis for on-chip variation (OCV), clock uncertainty and signal integrity (SI); power-reduction techniques to save both static and dynamic power; and yield optimization techniques such as preferred metal fill, multi-cut vias, wire spreading and lithographic hot-spot prevention.

The Cadence reference methodology for the Cortex-A9 processor that was produced from the ARM and Cadence collaboration will be well received by industry-leading companies who are deploying these reference methodologies and implementing designs using a Cortex-A9 processor with an automated, fully integrated design flow.

"As a leader in the design of next-generation devices, NEC Electronics Europe applauds the continuing close collaboration between ARM and Cadence. These reference methodologies are an invaluable part of our design process," said Thomas Langfermann, senior manager of design services for NEC Electronics Europe. "The robust validation methodology incorporated in the silicon-ready flow will improve predictability and reduce our time to market."

"ARM and Cadence are collaborating to provide silicon-ready reference methodologies that can be quickly deployed by engineering teams seeking predictable design flows that deliver superior quality of silicon," said Chi-Ping Hsu, corporate vice president of Power Forward and general manager of IC Digital at Cadence. "The combination of the Encounter advanced technologies and the ARM Cortex-A9 reference methodologies provides designers a complete solution to address the complexities and interdependent needs of low power and new process nodes."

"ARM continues to work with Cadence to provide reference methodologies for our mutual customers," said Peter Middleton, vice president of engineering, Processor Division, ARM. "We are now working with Cadence to extend the flow to incorporate additional low power management capabilities documented in the new chapter that ARM has contributed to the industry publication, A Practical Guide to Low-Power Design."

Cadence will continue to share the results of the Cortex-A9 collaboration through joint seminars and papers presented at events such as CDNLive! EMEA 2008, as well as through low-power techtorials and presentations at Cadence Technology on Tour events.

About the Practical Guide to Low-Power Design
"A Practical Guide to Low-Power Design — User Experience with CPF" was published by the Power Forward Initiative in March 2008 and has been downloaded by more than 1700 times. This continually updated online guide includes chapters contributed by Power Forward Initiative members on their experience with CPF-enabled low power design. The guide is available to designers through the Power Forward Initiative website at www.powerforward.org.