Taipei, Taiwan - March 18, 2008 - Alchip Technologies, Inc., a leading open foundry fabless ASIC provider, today announced it has joined the Power Forward Initiative (PFI). Alchip has deployed the Cadence® Design Systems, Inc. (NASDAQ: CDNS) Low-Power Solution and uses the Common Power Format (CPF) based solution to increase productivity and accelerate time-to-market for its customers.

"Low-power design is critical for multimedia, wireless and communication applications that are a focus for Alchip's customers," said Jim Bailey, Chief Operating Officer of Alchip. "We have a consistent track record of first silicon success and customers rely on us to deliver their ASICs on time. Customers view Alchip as a trusted silicon partner enabling them to realize their innovations. We provide many advantages including delivering the most area and power optimized consumer applications. Incorporating CPF will allow Alchip to unambiguously receive low-power intent from our customers, ensuring Alchip meets our customers?low power design goals on time."

"We welcome Alchip to the Power Forward Initiative and look forward to their contribution in reducing the barriers for low power IC design," said Pankaj Mayor, Group Director Business Enablement at Cadence."We commend Alchip for their leadership and commitment in recognizing the need to make low power design easier at advanced nodes. Their participation reinforces the need for the semiconductor industry to work collaboratively to advance the state-of-the-art of low power design."

CPF, a Si2-approved standard format, is used for specifying power-saving techniques early in the design process-enabling sharing and reuse of low-power intelligence throughout the design process. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format.

About Power Forward Initiative
The Power Forward Initiative, which has more than 20 member companies, is an industry initiative sponsored by Cadence that was formed in May 2006. It has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006 and CPF 1.0 is now available as an Si2 standard to the industry at large.

About Alchip®
Alchip Technologies, Inc., headquartered in Taipei, Taiwan, is a provider of silicon design and manufacturing services for companies developing complex and high-volume system-on-chip (SoC) designs. Founded in 2002 by semiconductor veterans from Silicon Valley and Japan, Alchip provides services intended to enable customers to cost-effectively address increasing technological complexity of silicon design and the need to reduce time to market. Alchip targets customers that address rapidly growing and high-volume end markets, such as entertainment devices, mobile phones, HDTV, communications equipment, computers and other consumer electronic products. Alchip has provided design services on numerous complex SoC devices at 130nm, 90nm and 65nm advanced process technologies. Alchip has branch offices in the U.S. (Santa Clara, CA), Japan (Shin-Yokohama), China (Shanghai), and Taiwan (Hsinchu). Additional information about Alchip is available at http://www.alchip.com.