Second Annual Silicon Valley PFI Low-Power Design Summit

Power Forward — Mon, 13 Jul 2009 06:52:00 GMT

Proceedings from all sessions at the 2009 PFI Low-Power Design Summit are now available in both PDF and video formats.

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(Note: PFI site membership is required to access the proceedings. Log in or register here.)

Agenda*

8:30am	Registration and Breakfast
9:00am	Introduction – Steve Carlson, Cadence
9:05am	Welcome Address – John Bruggeman, Cadence
9:20am	GUC Low Power Design Platform – Albert Li, Global Unichip
9:50am	Toward Interoperable Power Formats – Qi Wang, Si2
10:20am	Break
10:30am	Ulterior UMCL65SP ARM1176JZFSTM Low Power Results and Analysis – Sachin Idgunji, ARM; Please send an email to info@powerforwrad.org for details
11:00am	Cadence Low-Power Solution: Spec to GDSII – Kumar Subramani, Cadence
11:30am	Industry Insight Panel: The Low-Power Evolution; Challenges and Opportunities Moderator: Richard Goering, Cadence Panelists: Steve Presant, AMD, Steve Carlson, Cadence, Scott Evans, Sonics, Ron Burns, Wipro
12:15pm	Lunch (Cafeteria)
	PRE-SELECTED TRACKS
	Track: Design and Verification (Auditorium)
1:00pm	Sequential Optimizations for Low Power Design – Anmol Mathur, Calypto
1:30pm	Freescale Low Power Design Challenges – Magdy Abadir, Freescale
2:00pm	High Level Synthesis Using C-to-Silicon Compiler: A Case Study of Control-Dominated Design – Michael McNamara, Cadence
2:30pm	Break
2:45pm	Power-Aware Interface – Santosh Shivadatta, Mindtree
3:15pm	Supporting CPF for Highly-Configurable Interconnect IP – Scott Evans, Sonics
3:45pm	Q&A Panel Moderated by Mike Carrell, Cadence Panelists: Anmol Mathur, Calypto, Michael McNamara, Cadence, Magdy Abadir, Freescale Semiconductor, Arvind Chopra, NXP, Scott Evans, Sonics;
	Track: Implementation and Signoff (Kirra Point)
1:00pm	Implementation of Advanced Power-Aware Memory Compilers – Lisa Minwell, Virage Logic;
1:30pm	Power-Aware DFT & Test – Albert Chen, Faraday Semiconductor
2:00pm	Power-Optimization using Standard Cell Logic Blocks – Ken Brock, Virage Logic
2:30pm	Break
2:45pm	High Performance Low Power Clock Tree Architecture – Bob Eisenstadt, Alchip
3:15pm	TeraWatts to PicoWatts, A Low Power Perspective – Robert Smith, Magma
3:45pm	Q&A Panel Moderated by Anthony Williams, Cadence Panelists: Bob Eisenstadt, Alchip, Albert Chen, Faraday Semiconductor, Robert Smith, Magma, Ken Brock and Lisa Minwell, Virage Logic
4:15pm	Closing Remarks / Networking Reception (Auditorium)

Events : PFI Members

Second Annual Silicon Valley PFI Low-Power Design Summit

Go to the proceedings >>

Go to the proceedings >>