Events

System-level Design and Chip Architecture for Low-Power ICs Techtorial & Workshop

2009-07-29T17:13:00Z

Decisions and tradeoffs made during the early, pre-synthesis stages of the design cycle ultimately yield the greatest impact on the size, power consumption, performance, and cost of any SoC. It is during these early stages that design teams realize the greatest benefits by carefully analyzing and characterizing tradeoffs among different system-architecture and micro-architecture options.

As the recognized industry leader in automation of advanced low-power design techniques, Cadence has driven innovation and industry awareness of these techniques through its work in the Power Forward Initiative (www.powerforward.org). Cadence has recently extended its low-power support to Cadence system-level planning/design/analysis tools--InCyte Chip Estimator, C-to-Silicon Compiler, and Palladium Dynamic Power Analysis. These tools working in concert enable designers to plan the area, timing and power of a design. They can then feed optimized RTL and design-constraints into Cadence® Encounter® RTL Compiler, and utilize its design exploration capabilities for micro-architecture optimization.

This techtorial and workshop provides an in-depth survey of Cadence system-level design low-power solution, and gives designers an opportunity to "test-drive" these tools on actual designs.

Who should attend?

The techtorial portion (morning) is intended for system and chip architects, designers and technically oriented managers wanting a technical overview of how Cadence tools work together to enable low power design. The lab/workshop portion (afternoon) is geared toward experienced system and chip architects and hardware designers wanting a "hands-on" opportunity to apply the concepts/tools discussed in the morning on actual designs.

What you will learn

The techtorial/workshop will cover the Cadence System-Level and Chip Architecture Low-Power Design solution and will educate the audience about how to:

Estimate IC size, power, leakage, performance and cost with InCyte Chip Estimator to rapidly analyze options across design architecture, IP, and manufacturing processes pre-RTL and establish the design specifications for downstream implementation steps
Transform re-usable C/C++/SystemC models into optimized synthesizable RTL with power, area, and performance micro-architecture tradeoffs, using Cadence C-to-Silicon Compiler
Analyze dynamic power consumption using real-world stimulus across the different elements of your design using Cadence Palladium DPA
Explore performance, power, and area of different power architectures using RTL and constraints to refine the chip architecture before synthesis, using RTL Compiler design exploration capabilities

More information and registration >>

System-level Design and Chip Architecture for Low-Power ICs Techtorial & Workshop

2009-07-29T00:57:00Z

Who should attend?

What you will learn

The techtorial/workshop will cover the Cadence System-Level and Chip Architecture Low-Power Design solution and will educate the audience about how to:

Estimate IC size, power, leakage, performance and cost with InCyte Chip Estimator to rapidly analyze options across design architecture, IP, and manufacturing processes pre-RTL and establish the design specifications for downstream implementation steps
Transform re-usable C/C++/SystemC models into optimized synthesizable RTL with power, area, and performance micro-architecture tradeoffs, using Cadence C-to-Silicon Compiler
Analyze dynamic power consumption using real-world stimulus across the different elements of your design using Cadence Palladium DPA
Explore performance, power, and area of different power architectures using RTL and constraints to refine the chip architecture before synthesis, using RTL Compiler design exploration capabilities

More information and registration >>

Cadence CDNLive! India 2009

2009-07-16T17:52:00Z

CDNLive! India brings together Cadence users, developers and industry experts to educate, inspire, and energize you. It offers a unique opportunity to investigate challenges and synthesize solutions with people, who like you, are excited about the latest in electronic design.

Whether you're an architect, IC or PCB design or layout engineer, verification or CAD engineer, or an engineering manager, you'll have the opportunity to interact with your peers using Cadence technology—and with the technologists who develop your tools.

We are looking for experts in electronic design to give presentations on a variety of topics including:

High-level and physical design methodologies
RTL-to-GDSII design flows
Low-power design and verification
System verification simulation
Analog, RF & mixed-signal design
PCB and packaging design
Design for manufacturing
Hardware assisted simulation and acceleration

And many more...

Take this opportunity to join other technology leaders and present a paper. Share your knowledge and expertise with the semiconductor design community.

2009 Conference Highlights

Papers: Choose from papers addressing all aspects of digital design, low power, verification, implementation, custom design, and PCB design—from today's successes to tomorrow's possibilities. Power users and Cadence experts share their results and explain how they used Cadence technology to their advantage.

Keynote Speakers: Hear from industry leaders who influence change and drive innovation in the global electronics marketplace. Keynote speakers will address product announcements and discuss industry trends to help you prepare for the future.

Canvas Conversations: Chat with authors of some of the highest quality conference paper submissions.

Designer Expo: Explore new solutions from a variety of exhibitors and learn about the solutions they have developed jointly with Cadence. Find out how others are using Cadence technology to free up engineering resources for what matters most—innovation.

Second Annual Silicon Valley PFI Low-Power Design Summit

2009-07-13T06:52:00Z

Proceedings from all sessions at the 2009 PFI Low-Power Design Summit are now available in both PDF and video formats.

Go to the proceedings >>

(Note: PFI site membership is required to access the proceedings. Log in or register here.)

Agenda*

8:30am	Registration and Breakfast
9:00am	Introduction – Steve Carlson, Cadence
9:05am	Welcome Address – John Bruggeman, Cadence
9:20am	GUC Low Power Design Platform – Albert Li, Global Unichip
9:50am	Toward Interoperable Power Formats – Qi Wang, Si2
10:20am	Break
10:30am	Ulterior UMCL65SP ARM1176JZFSTM Low Power Results and Analysis – Sachin Idgunji, ARM; Please send an email to info@powerforwrad.org for details
11:00am	Cadence Low-Power Solution: Spec to GDSII – Kumar Subramani, Cadence
11:30am	Industry Insight Panel: The Low-Power Evolution; Challenges and Opportunities Moderator: Richard Goering, Cadence Panelists: Steve Presant, AMD, Steve Carlson, Cadence, Scott Evans, Sonics, Ron Burns, Wipro
12:15pm	Lunch (Cafeteria)
	PRE-SELECTED TRACKS
	Track: Design and Verification (Auditorium)
1:00pm	Sequential Optimizations for Low Power Design – Anmol Mathur, Calypto
1:30pm	Freescale Low Power Design Challenges – Magdy Abadir, Freescale
2:00pm	High Level Synthesis Using C-to-Silicon Compiler: A Case Study of Control-Dominated Design – Michael McNamara, Cadence
2:30pm	Break
2:45pm	Power-Aware Interface – Santosh Shivadatta, Mindtree
3:15pm	Supporting CPF for Highly-Configurable Interconnect IP – Scott Evans, Sonics
3:45pm	Q&A Panel Moderated by Mike Carrell, Cadence Panelists: Anmol Mathur, Calypto, Michael McNamara, Cadence, Magdy Abadir, Freescale Semiconductor, Arvind Chopra, NXP, Scott Evans, Sonics;
	Track: Implementation and Signoff (Kirra Point)
1:00pm	Implementation of Advanced Power-Aware Memory Compilers – Lisa Minwell, Virage Logic;
1:30pm	Power-Aware DFT & Test – Albert Chen, Faraday Semiconductor
2:00pm	Power-Optimization using Standard Cell Logic Blocks – Ken Brock, Virage Logic
2:30pm	Break
2:45pm	High Performance Low Power Clock Tree Architecture – Bob Eisenstadt, Alchip
3:15pm	TeraWatts to PicoWatts, A Low Power Perspective – Robert Smith, Magma
3:45pm	Q&A Panel Moderated by Anthony Williams, Cadence Panelists: Bob Eisenstadt, Alchip, Albert Chen, Faraday Semiconductor, Robert Smith, Magma, Ken Brock and Lisa Minwell, Virage Logic
4:15pm	Closing Remarks / Networking Reception (Auditorium)

Go to the proceedings >>

Cadence CDNLive! Israel 2009

2009-06-28T05:46:00Z

CDNLive! Israel 2009 is the Cadence Israel annual event that brings together Cadence® technology users, developers, and industry experts to educate and energize you.

CDNLive! Israel offers you the opportunity to investigate challenges and synthesize solutions with people who, like you, are excited about trends and possibilities in electronic design.

Find out the latest insights on complex design issues, solutions to address the anticipated design challenges of tomorrow, as well as practical techniques and tips from other power users and Cadence technologists to enhance your design skills.

By attending the large variety of technical papers submitted by engineers in similar fields, CDNLive! participants will find solutions to their own design challenges.

In addition, with keynote presentations and technical presentations led by notable executives in the electronics industry, CDNLive! Israel 2009 is set to generate a great deal of excitement and will be the highlight EDA user event of the year.

More info at: http://www.cadence.com/cdnlive/il/2009/pages/default.aspx