Decisions and tradeoffs made during the early, pre-synthesis stages of the design cycle ultimately yield the greatest impact on the size, power consumption, performance, and cost of any SoC. It is during these early stages that design teams realize the greatest benefits by carefully analyzing and characterizing tradeoffs among different system-architecture and micro-architecture options.

As the recognized industry leader in automation of advanced low-power design techniques, Cadence has driven innovation and industry awareness of these techniques through its work in the Power Forward Initiative (www.powerforward.org). Cadence has recently extended its low-power support to Cadence system-level planning/design/analysis tools--InCyte Chip Estimator, C-to-Silicon Compiler, and Palladium Dynamic Power Analysis. These tools working in concert enable designers to plan the area, timing and power of a design. They can then feed optimized RTL and design-constraints into Cadence® Encounter® RTL Compiler, and utilize its design exploration capabilities for micro-architecture optimization.

This techtorial and workshop provides an in-depth survey of Cadence system-level design low-power solution, and gives designers an opportunity to "test-drive" these tools on actual designs.