As the industry pushes toward increased mobility, higher integration, smaller process geometries and green design – the existing design infrastructure must be upgraded to enable power efficient design techniques. Power-control methods, when used, are implemented in an ad-hoc way significantly increasing the potential for higher risk and cost.
Across the ECO system, an urgent need has emerged for a comprehensive approach to power-efficient design. To facilitate and support this new era of design innovation, Cadence and its partners formed the Power Forward Initiative (PFI).
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative created a systematic, integrated approach to power-efficient and low-power design, providing a platform for higher-level exploration and IP reuse. Power Forward Initiative participants created the Common Power Format (CPF) together with Si2 as an open specification language that captures all power-specific intent – including design, constraint, and functionality requirements in a single file.
By linking the silicon design chain, the Power Forward Initiative enables automation of power-reduction techniques and increases predictability and quality. No longer constrained by the complexity of power-efficient design, risk of low yield or costly respins, design teams can focus their time and resources on what matters most – innovation. Companies across a wide range of industries are now able to explore now application possibilities, start power-efficient design projects, and adopt new process geometries profitably.
With the support of participant companies, the Power Forward Initiative has established a new design infrastructure that removes barriers, spurs innovation, and delights mutual customers.