Open-Silicon

News

Cadence Design Systems to Host Second Annual Silicon Valley Power Forward Low-Power Design Summit
S3 Joins Power Forward Initiative
Cadence Low-Power Solution Selected for Global Unichip’s PowerMagic Low-Power Design Methodology
UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0

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Community

Open-Silicon provides leading edge SoC and ASIC IC design, open market IP integration, and high-quality silicon manufacturing services to customers worldwide. As a fabless company, Open-Silicon focuses on delivering the most cost-effective, predictable and reliable custom SoC solutions. We partner with customers using flexible models that sometimes include full turnkey development from spec handoffs, and sometimes include only manufacturing services to take advantage of our volume foundry, test, and packaging pricing. Since its founding in 2003, the company has focused on raising the bar on SoC execution, measuring the quality of our engineering work and our ability to hit customer schedules and reporting that to the board of directors at every board meeting. Our executive salaries are paid based upon those metrics, too, ensuring that the entire organization is focused on getting the customer's silicon built on time, and correctly. For additional information about Open-Silicon, visit www.open-silicon.com.

Advisors

Colin Baldwin
Director of Marketing
Open-Silicon, Inc.

Colin Baldwin joined Open-Silicon in 2006 and currently serves as the director of marketing and business development. He has 17 years of experience with IBM, Texas Instruments, Arrow Electronics, and Open-Silicon. He has held a variety of positions including applications engineering manager, North American ASIC design center manager, and North American ASIC FAE manager. He has written papers and filed for patents on various subjects including digital signal processing, FPGA-to-ASIC conversion, and various aspects of ASIC design. He received both BEE and MSEE degrees from Georgia Tech.